M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 282

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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16.3 I
e
E
1
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J
6
0
The S20 register is used to set theACK control, SCL mode and the SCL frequency.
16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)
16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE)
16.3.3 Bit 6: ACK Bit (ACKBIT)
16.3.4 Bit 7: ACK Clock Bit (ACK-CLK)
C
2
9
These bits control the SCL frequency. See Table 16.3 .
The FAST MODE bit selects SCL mode. When the FAST MODE bit is set to "0", standard clock mode
is entered. When it is set to "1", high-speed clock mode is entered.
When using the high-speed clock mode I
set the FAST MODE bit to "1" (select SCL mode as high-speed clock mode) and use the I
system clock (V
The ACKBIT bit sets the SDA status when an ACK clock
to “0”, ACK is returned and te clock applied to SDA becomes "L" when ACK clock is generated. When
it is set to "1", ACK is not returned and the clock clock applied to SDA maintains "H" at ACK clock
generation.
When the ACKBIT bit is set to "0", the address data is received. When the slave address matches with
the address data, SDA becomes "L" automatically (ACK is returned). When the slave address and the
address data are not matched, SDA becomes "H" (ACK is not returned).
The ACK-CLK bit set a clock for data transfer acknowledgement. When the ACK-CLK bit is set to "0",
ACK clock is not generated after data is transferred. When it is set to "1", a master generates ACK
clock every one-bit data transfer is completed. The device, which transmits address data and control
data, leave SDA pin open (apply "H" signal to SDA) when ACK clock is generated. The device which
receives data, receives the generated ACKBIT bit.
0 .
B
2 /
NOTES:
0
0
NOTES:
8
0
1. ACK clock: Clock for acknowledgment
2
4
J
G
1.Do not rewrite the S20 register, other than the ACKBIT bit during data transfer. If data is written
7
a
C0 Clock Control Register (S20 register)
o r
0 -
. n
to other than the ACKBIT bit during transfer, the I
not be transferred successfully.
u
2
3
0
p
, 1
0
(
M
2
0
1
0
6
7
IIC
C
2 /
) at 4 MHz or more frequency.
page 260
, 8
M
1
6
C
f o
2 /
8
3
) B
8
5
2
C bus standard (400 kbits/s maximum) to connect buses,
2
C bus clock circuit is reset and the data may
(1)
is generated. When the ACKBIT bit is set
16. MULTI-MASTER I
2
C bus INTERFACE
2
C bus