M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 209

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 14.17 Receive Operation
Table 14.9 Example of Bit Rates and Settings
. v
6
J
0
C
Bit Rate
2
9
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
2 /
UiC1 register
RE bit
RxDi
Transfer clock
SiRIC register
IR bit
UiBRG count
source
RTSi
UiC1 register
RI bit
0 .
The above timing diagram applies to the case where the register bits are set as follows:
(bps)
B
14400
19200
28800
31250
38400
51200
i = 0 to 2
14.1.2.1 Bit Rates
1200
2400
4800
9600
8
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
0
0
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 14.9 lists example of bit rate and settings.
0
G
4
J
7
a
o r
0 -
. n
u
2
p
3
0
Count Source
, 1
0
(
M
2
of BRG
1
0
0
6
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“H”
7
C
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
2 /
Reception triggered when transfer clock
is generated by falling edge of start bit
, 8
page 187
M
1
6
C
Peripheral Function Clock : 16MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
2 /
f o
Start
8
103(67h)
103(67h)
bit
3
) B
31(1Fh)
51(33h)
25(19h)
68(44h)
51(33h)
34(22h)
25(19h)
19(13h)
8
5
Sampled “L”
Cleared to “0” when interrupt request is accepted, or cleared to “0” by program
D
0
Receive data taken in
14493
19231
28571
31250
38462
50000
1202
2404
4808
9615
Transferred from UARTi receive
register to UiRB register
D
1
Peripheral Function Clock : 20MHz
D
7
129(81h)
129(81h)
42(2Ah)
64(40h)
32(20h)
86(56h)
64(40h)
39(27h)
32(20h)
24(18h)
Stop bit
Read out from
UiRB register
14368
19231
29070
31250
37879
50000
1202
2404
4735
9615
14. Serial I/O