MC9S12GC96MFAE Freescale Semiconductor, MC9S12GC96MFAE Datasheet - Page 584
![IC MCU 96K FLASH 25MHZ 48-LQFP](/photos/12/19/121954/mc9s12gc96mfae_sml.jpg)
MC9S12GC96MFAE
Manufacturer Part Number
MC9S12GC96MFAE
Description
IC MCU 96K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12GC96MFAE
Manufacturer:
FRE/MOT
Quantity:
20 000
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1)
20.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
20.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but not writable.
The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence,
indicated by F in
584
Module Base + 0x0000
Module Base + 0x0001
FDIV[5:0]
FDIVLD
PRDIV8
Reset
Reset
Field
5–0
7
6
W
W
R
R
KEYEN1
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written to since the last reset
Enable Prescalar by 8
0 The oscillator clock is directly fed into the Flash clock divider
1 The oscillator clock is divided by 8 before feeding into the Flash clock divider
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to
FCLKDIV Register”
Flash Clock Divider Register (FCLKDIV)
Flash Security Register (FSEC)
F
0
7
7
Figure
= Unimplemented or Reserved
= Unimplemented or Reserved
KEYEN0
PRDIV8
20-7.
0
F
6
6
Figure 20-6. Flash Clock Divider Register (FCLKDIV)
for more information.
Figure 20-7. Flash Security Register (FSEC)
Table 20-4. FCLKDIV Field Descriptions
FDIV5
MC9S12C-Family / MC9S12GC-Family
NV5
0
F
5
5
FDIV4
Rev 01.24
NV4
0
F
4
4
Description
FDIV3
NV3
F
0
3
3
FDIV2
NV2
0
F
2
2
Section 20.4.1.1, “Writing the
Freescale Semiconductor
FDIV1
SEC1
0
F
1
1
FDIV0
SEC0
F
0
0
0
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