M37542F8FP#U0 Renesas Electronics America, M37542F8FP#U0 Datasheet - Page 31

• Manufacturer Part Number: M37542F8FP#U0
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7542 Group
Fig. 26 Interrupt sequence
Fig. 27 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Rev.3.03
REJ03B0006-0303
Internal clock φ
SYNC
Jul 11, 2008
Address bus
SYNC : CPU operation code fetch cycle
B
A
SPS
Data bus
L
L
, B
, A
SYNC
H
H
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
WR
RD
φ
: Vector address of each interrupt
: Jump destination address of each interrupt
: “00
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
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(This is an internal signal that cannot be observed from the external unit.)
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
T1
16
” or “01
PC
Not used
Instruction cycle
16
”
S,SPS
PC
IR1 T2
Push onto stack
S-1,SPS S-2,SPS
Vector fetch
H
PC
L
PS
Push onto stack
B
Vector fetch
L
A
L
B
H
A
H
Execute interrupt
routine
A
L
,A
H
IR2 T3
Instruction cycle