M37542F8FP#U0 Renesas Electronics America, M37542F8FP#U0 Datasheet
M37542F8FP#U0
Specifications of M37542F8FP#U0
Available stocks
Related parts for M37542F8FP#U0
M37542F8FP#U0 Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7542 Group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 7542 Group has serial interfaces, 8-bit timers, 16-bit timers, and an A/D converter, and is useful for ...
Page 4
Group PIN CONFIGURATION (TOP VIEW) P0 (LED /CNTR Fig. 1 Pin configuration (Package type: PLQP0032GB- CLK1 RDY1 P1 /CNTR ...
Page 5
Group P1 Fig. 3 Pin configuration (Package type: PRDP0032BA-A) P0 (LED )/ CLK2 P0 (LED )/ RDY2 P1 /RxD /CAP /TxD CLK1 RDY1 P1 /CNTR ...
Page 6
Group P1 /CNTR / / / / / / / / REF RESET CNV Vcc X ...
Page 7
Group Table 1 Performance overview Parameter Number of basic instructions Instruction execution time Oscillation frequency Memory sizes Mask ROM ROM RAM FLASH ROM ROM RAM I/O port P0, P1, P2, P3 Interrupts Timer Output compare Input capture Serial interface ...
Page 8
Group FUNCTIONAL BLOCK Fig. 6 Functional block diagram (Package type: PLQP0032GB-A) Rev.3.03 Jul 11, 2008 Page 6 of 117 REJ03B0006-0303 ...
Page 9
Group Fig. 7 Functional block diagram (Package type: PRSP0036GA-A) Rev.3.03 Jul 11, 2008 Page 7 of 117 REJ03B0006-0303 ...
Page 10
Group Fig. 8 Functional block diagram (Package type: PRDP0032BA-A) Rev.3.03 Jul 11, 2008 Page 8 of 117 REJ03B0006-0303 ...
Page 11
Group Fig. 9 Functional block diagram (Package type: PWQN0036KA-A) Rev.3.03 Jul 11, 2008 Page 9 of 117 REJ03B0006-0303 ...
Page 12
Group PIN DESCRIPTION Table 2 Pin description Pin Name Vcc, Vss Power source Mask ROM version FLASH ROM version V Analog refer- •Reference voltage input pin for A/D converter. REF ence voltage CNVss CNVss •Chip operating mode control pin, ...
Page 13
Group GROUP EXPANSION Renesas plans to expand the 7542 group as follow: Memory type Support for Mask ROM version, Flash memory version, and Emu- lator MCU . ROM size (bytes) 32K +4K 16K +4K 16K 8K M37542M2 0 384 ...
Page 14
Group Currently supported products are listed below. Table 3 List of supported products ROM size (bytes) Product ROM size for User ( ) M37542M2-XXXSP 8192 M37542M2-XXXHP (8062) M37542M2-XXXFP M37542M2-XXXGP M37542M4-XXXSP 16384 M37542M4-XXXHP (16254) M37542M4-XXXFP M37542M4-XXXGP M37542F4SP 16384 + 4096 ...
Page 15
Group FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL for details on each ...
Page 16
Group M (S) (S) Store Return Address on Stack M (S) (S) Subroutine Execute RTS (S) Restore Return Address (PC (S) (PC Note : The condition to enable the interrupt Fig. 12 Register push and pop at interrupt generation ...
Page 17
Group Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero ...
Page 18
Group [CPU mode register] CPUM The CPU mode register contains the stack page selection bit, etc.. This register is allocated at address 003B Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of ...
Page 19
Group Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and ...
Page 20
Group Port P0 (P0) 0000 16 0001 Port P0 direction register (P0D) 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 16 Port P3 ...
Page 21
Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corre- sponds to one pin, and each pin can be set to ...
Page 22
Group Table 6 I/O port function table Pin Name P0 (LED )/CAP I/O port P0 •CMOS compatible input level (Note 1) •CMOS 3-state output P0 (LED )/CMP (LED )/CMP ...
Page 23
Group (1) Port P0 0 Pull-up control Direction register Port latch Data bus Capture 0 input Capture 0 input control To key input interrupt generating circuit (3) Port P0 3 Pull-up control P0 /TX output valid 3 OUT Direction ...
Page 24
Group (8) Port P1 0 Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch Serial I/O1 input Capture 0 input control Capture 0 input (10) Port P1 2 Serial I/O1 synchronous clock selection bit Serial ...
Page 25
Group (14) Port P3 0 Direction register Data bus Port latch Capture 1 input Capture 1 input control (16) Port P3 3 Direction register Data bus Port latch INT input control 1 INT input 1 (18) Port P3 6 ...
Page 26
Group Termination of unused pins • Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow ...
Page 27
Group Interrupts The 7542 Group interrupts are vector interrupts with a fixed prior- ity scheme, and generated by 16 sources among 18 sources: 6 external, 11 internal, and 1 software. The interrupt sources, vector addresses are shown in Table ...
Page 28
Group Interrupt request bit Interrupt enable bit Interrupt disable flag I Fig. 23 Interrupt control • Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor sta- tus register. This flag controls the acceptance ...
Page 29
Group b7 b0 Interrupt source set register (INTSET: address 000A Key-on wakeup interrupt valid bit UART1 bus collision detection interrupt valid bit A/D conversion interrupt valid bit Timer 1 interrupt valid bit Not used (returns “0” when read) 0: ...
Page 30
Group • Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (ex- ternal interrupt signal input, timer underflow, etc.) and the corresponding request ...
Page 31
Group φ SYNC RD WR Address bus Data bus SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit Vector address of each interrupt L ...
Page 32
Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words generated when the AND ...
Page 33
Group Timers The 7542 Group has 4 timers: timer 1, timer X, timer A and timer B. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. ...
Page 34
Group (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the sig- nal input to P1 /CNTR pin is measured The operation of Timer X can be controlled by the level ...
Page 35
Group 1/16 “00” “01” “11” Clock Frequency Timer X count division ratio divider source selection bits selection bits X 1/16 IN 1/2 On-chip 1/1 “10” oscillator CPU mode register CNTR active 0 edge switch bit P1 /CNTR 4 0 ...
Page 36
Group Timer A,B Timer A and Timer B are 16-bit timers and counts the signal which is the oscillation frequency selected by setting of the timer count source set register (TCSS). Timer A and Timer B have the same ...
Page 37
Group ...
Page 38
Group Output compare 7542 group has 4-output compare channels. Each channel ( has the same function and can be used to output waveform by us- ing count value of either Timer A or Timer B. The source ...
Page 39
Group ...
Page 40
Group P0 /CMP 1 0 Wave latch channel 0 Compare 0 timer source bit Compare channel 0 Compare channel 1 P0 /CMP 2 1 Compare channel 2 P3 /CMP 1 2 Compare channel 3 P3 /CMP 2 3 Fig. ...
Page 41
Group I/O P0 /CMP 1 0 port Compare 0 output port bit (001E , bit 2) 16 Compare 0 output status bit (0022 , bit 0) 16 Compare 0 output level latch (0021 , bit 0) 16 Compare 1 ...
Page 42
Group Timer count clock Timer underflow Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare output Compare interrupt Compare status ...
Page 43
Group Carrier wave generated by Compare 0 Timer A count clock Timer A underflow Timer A count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 Compare latch 00 Compare latch 01 Compare 00 match ...
Page 44
Group 1. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Positive”. Compare 0 output Compare 1 output Modulation output 2. When Compare 0 output level latch is “Negative”, Compare 1 output level latch ...
Page 45
Group Input capture 7542 group has 2-input capture channels. Each channel (0 and 1) has the same function and can be used to capture count value of either Timer A or Timer B. The source timer for each channel ...
Page 46
Group ...
Page 47
Group P0 /CAP 0 0 Trigger input channel 0 P1 /CAP 0 0 Ring /512 Capture 0 timer source bit P3 /CAP 0 1 Capture channel 0 Ring Capture channel 1 /512 Fig. 51 Block diagram of input capture ...
Page 48
Group Timer underflow Capture input wave Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 Capture latch 00 XXXX Capture latch 01 Capture interrupt Capture x (x=0, 1) status bit 1 Fig. 53 ...
Page 49
Group Serial Interface The 7542 Group has Serial I/O1 and Serial I/O2. Except that Serial I/O1 has the bus collision detection function and the T structure for Serial I/O2 is CMOS only, they have the same function. Serial I/O1 ...
Page 50
Group (2) Asynchronous Serial I/O1 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be ...
Page 51
Group [Transmit buffer register 1/receive buffer register 1 (TB1/ RB1)] 0018 16 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. ...
Page 52
Group ...
Page 53
Group Bus collision detection (SIO1) SIO1 can detect a bus collision by setting UART1 bus collision de- tection interrupt enable bit. When transmission is started in the clock synchronous or asyn- chronous (UART) serial I/O mode, the transmit pin ...
Page 54
Group Serial I/O2 Serial I/O2 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
Page 55
Group (2) Asynchronous Serial I/O2 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O2 mode selection bit of the serial I/O2 control register to “0”. Eight serial data transfer formats can be ...
Page 56
Group [Transmit buffer register 2/receive buffer register 2 (TB2/ RB2)] 002E 16 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. ...
Page 57
Group ...
Page 58
Group A/D Converter The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during ...
Page 59
Group Data bus A/D control register (Address 0034 /AN 7 ...
Page 60
Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H ...
Page 61
Group Reset Circuit The 7542 group starts operation by the on-chip oscillator after sys- tem is released from reset. Accordingly, when the rising of power supply voltage passes 2.2V, set the reset input voltage to become below 0.2Vcc (0.44V). ...
Page 62
Group (1) Port P0 direction register (P0D) (2) Port P1 direction register (P1D) (3) Port P2 direction register (P2D) (4) Port P3 direction register (P3D) (5) Interrupt source set register (INTSET) (6) Interrupt source discrimination register (INTDIS) (7) Compare ...
Page 63
Group Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator be- tween X and X , and an RC oscillation circuit can be formed IN OUT by connecting a resistor and a capacitor. Use the ...
Page 64
Group (1) Oscillation control • Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level and the X oscillator stops. At this time, timer 1 is set IN to “01 ” and ...
Page 65
Group On-chip oscillation division ratio At on-chip oscillator mode, division ratio of on-chip oscillator for CPU clock is selected by setting value of on-chip oscillation divi- sion ratio selection register. The division ratio of on-chip oscillation for CPU clock ...
Page 66
Group (Note) On-chip oscillator mode On-chip oscillator Q S STP instruction R Reset Interrupt disable flag l Interrupt request Note: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. ...
Page 67
Group Interrupt f(X ) oscillation: enabled f(X IN On-chip oscillator: stop On-chip oscillator: enabled WAIT mode 1 Interrupt WIT instruction CPUM = State 1 CPUM = f(X On-chip oscillator: enabled Oscillation stop detection circuit valid ...
Page 68
Group Oscillation stop detection circuit The oscillation stop detection circuit is used to detect an oscilla- tion stop when a ceramic resonator or oscillation circuit stops due to disconnection. To use the oscillation stop detection circuit, set the on-chip ...
Page 69
Group f(X ) oscillation: enabled IN State 2 On-chip oscillator: enabled MISRG = MISRG = (MISRG is cleared to “0”.) 3 f(X ) oscillation: enabled IN State 2’ On-chip oscillator: enabled State 2’a (Note 5) ...
Page 70
Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, ...
Page 71
Group NOTES ON USE Countermeasures against noise 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. <Reason> The wiring length depends on a microcomputer package. Use of a small package, ...
Page 72
Group 2. Connection of bypass capacitor across V Connect an approximately 0.1 µ F bypass capacitor across the V line and the V line as follows: CC • Connect a bypass capacitor across the V at equal length. • ...
Page 73
Group 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a mi- crocomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an ...
Page 74
Group 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware> • Connect a resistor of 100 Ω or more to an I/O port in series. <Software> • As for an input port, read ...
Page 75
Group FLASH MEMORY MODE The 7542 group’s flash memory version has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and ...
Page 76
Group 32K bytes ROM Product 0000 16 SFR area 7000 16 0040 16 Internal RAM area RAM 7800 16 (1K bytes) 043F 16 8000 16 0FE0 16 SFR area 0FFF 16 7000 16 Internal flash memory area (4K bytes) ...
Page 77
Group [Flash memory control registers (FMCR0 to FMCR2)] 0FE0 to 0FE2 16 16 Figure 98 shows the flash memory control register 0. Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to ...
Page 78
Group Figure 99 shows the flash memory control register 1. Bit 0 of the flash memory control register 1 is the Erase suspend enable bit. By setting this bit to “1”, the erase suspend mode to suspend erase processing ...
Page 79
Group Figure 101 shows a flowchart for setting/releasing CPU rewrite mode ...
Page 80
Group Software Commands Table 11 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a soft- ware command to specify an erase or program operation. Each software command is explained below. • Read ...
Page 81
Group • Block Erase Command (20 / writing the command code “20 ” in the first bus cycle and the 16 confirmation command code “D0 ” and the block address in the 16 second bus ...
Page 82
Group Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the following ways: (1) By reading an arbitrary ...
Page 83
Group Full Status Check By performing full status check possible to know the execu- tion results of erase and program operations. Figure 104 shows a full status check flowchart and the action to be taken when each ...
Page 84
Group Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ...
Page 85
Group (2) ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared with the ID code written ...
Page 86
Group Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 7542 Group (flash ...
Page 87
Group Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode ...
Page 88
Group (1) Standard serial I/O mode 1 Table 13 Description of pin function (standard serial I/O mode 1) Pin name Signal name V ,V Power supply CC SS CNV CNV SS SS RESET Reset input X Clock input IN ...
Page 89
Group RxD TxD S CLK BUSY P0 (LED )/ RDY2 /CAP CLK1 RDY1 P1 /CNTR ...
Page 90
Group CLK1 RDY1 P1 /CNTR / / / / / / /AN ...
Page 91
Group • Standard serial I/O mode 1 Figure 110 shows the handling example of control pins on the user system board when the standard serial I/O mode 1 is used. Refer to the serial programmer manual of your programmer ...
Page 92
Group Power source RESET CNV SS P3 (RP (CEB (BUSY CLK2 P0 (TxD ) (RxD ) 4 2 Symbol Ratings Min. Typ. td(port-CNVss ...
Page 93
Group (2) Standard serial I/O mode 2 Table 14 Description of pin function (standard serial I/O mode 2) Pin name Signal name V ,V Power supply CC SS CNV CNV SS SS RESET Reset input X Clock input IN ...
Page 94
Group RxD TxD input "L" BUSY P0 (LED )/ RDY2 /CAP CLK1 RDY1 P1 /CNTR ...
Page 95
Group CLK1 RDY1 P1 /CNTR / / / / / / /AN ...
Page 96
Group • Standard serial I/O mode 2 Figure 115 shows the handling example of control pins on the user system board when the standard serial I/O mode 2 is used. Refer to the serial programmer manual of your programmer ...
Page 97
Group Power source RESET CNV SS P3 (RP (CEB CLK2 P0 (TxD ) (RxD ) 4 2 Symbol Ratings Min. Typ. td(port-CNVss td(CNVss-RESET th(RESET-CNVss) 1 ...
Page 98
Group ELECTRICAL CHARACTERISTICS 1.Absolute Maximum Ratings Table 15 Absolute maximum ratings Symbol Parameter V Power source voltage CC V Input voltage I P0 – – Input voltage RESET, X ...
Page 99
Group Recommended Operating Conditions Table 16 Recommended operating conditions (1) (FLASH ROM version 2.7 to 5.5V, Mask ROM version Symbol V Power source voltage (High-, Middle-speed mode) CC (ceramic) (Double-speed mode) Power source voltage (High-, ...
Page 100
Group Recommended Operating Conditions (continued) Table 17 Recommended operating conditions (2) (FLASH ROM version 2.7 to 5.5V, Mask ROM version Symbol “H” peak output current (Note 1) I OH(peak) “L” peak output current (Note 1) ...
Page 101
Group Electrical Characteristics Table 18 Electrical characteristics (1) (FLASH ROM version 2.7 to 5.5V, Mask ROM version Symbol Parameter V “H” output voltage OH P0 – – – ...
Page 102
Group Electrical Characteristics (continued) Table 19 Electrical characteristics (2) (FLASH ROM version 2.7 to 5.5V, Mask ROM version Symbol Parameter I Power source f MHz CC IN current Output transistors “off” f(X ...
Page 103
Group A/D Converter Characteristics Table 20 A/D Converter characteristics (V = 2 – °C, unless otherwise noted Symbol Parameter — Resolution — Absolute accuracy t Conversion ...
Page 104
Group Timing Requirements Table 22 Timing requirements (1) (FLASH ROM version 4.0 to 5.5V, Mask ROM version Symbol t (RESET) Reset input “L” pulse width External clock input cycle time C ...
Page 105
Group Table 24 Timing requirements (3) (Mask ROM version 2 Symbol t (RESET) Reset input “L” pulse width External clock input cycle time ...
Page 106
Group Switching Characteristics Table 25 Switching characteristics (1) (FLASH ROM version 4.0 to 5.5V, Mask ROM version Symbol Serial I/O1, serial I/O2 clock output “H” pulse width WH CLK1 ...
Page 107
Group CNTR 0 INT , INT 0 1 CAP , CAP 0 1 RESET CLK1 R D (at receive (at transmit Fig. 118 Timing chart Rev.3.03 Jul 11, 2008 Page ...
Page 108
Group PACKAGE OUTLINE JEITA Package Code RENESAS Code P-LQFP32-7x7-0.80 PLQP0032GB Index mark JEITA Package Code RENESAS Code P-SSOP36-8.4x15-0.80 PRSP0036GA Index mark Rev.3.03 Jul 11, 2008 ...
Page 109
Group JEITA Package Code RENESAS Code P-SDIP32-8.9x28-1.78 PRDP0032BA SEATING PLANE JEITA Package Code RENESAS Code P-HWQFN36-6x6-0.50 PWQN0036KA Rev.3.03 Jul 11, 2008 Page 107 of 117 ...
Page 110
Group APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a re- set. In particular essential to initialize the T and D flags ...
Page 111
Group 5. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (SFR). The read-modify-write instruction operates in the following se- quence: read one-byte of data from memory, modify the data, write the data back to ...
Page 112
Group 6. Direction register The values of the port direction registers cannot be read. That is impossible to use the LDA instruction, memory opera- tion instruction when the T flag is “1”, addressing mode using direction register ...
Page 113
Group 3. Interrupt discrimination bit Use an LDM instruction to clear to “0” an interrupt discrimination bit. LDM #%0000XXXX, $0B Set the following values to “X” “0”: an interrupt discrimination bit to clear “1”: other interrupt discrimination bits Ex.) ...
Page 114
Group Notes on Output Compare 1. When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously not write the same data to both ...
Page 115
Group Notes on Serial I/Oi (i= Clock synchronous serial I/O (1) When the transmit operation is stopped, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and transmit disabled). <Reason> Since ...
Page 116
Group Notes on Serial I/O1 1. I/O pin function when serial I/O1 is enabled. The pin functions and P1 2 CLK1 3 follows according to the setting values of a serial I/O1 mode selec- tion bit ...
Page 117
Group Notes on A/D conversion 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01µF to 1µF. Further, be sure to verify the operation ...
Page 118
Group Notes on Clock Generating Circuit 1. Switch of ceramic and RC oscillations After releasing reset, the oscillation mode selection bit (bit 5 of CPU mode register (address “0” (ceramic oscillation se- 16 lected). When the ...
Page 119
Group Notes on On-chip Oscillation Division Ratio • When the clock division ratio is switched from f(X oscillator by the clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B )), the on-chip oscillator ...
Page 120
REVISION HISTORY Rev. Date Page – First edition issued 1.00 Nov 27, 2002 1 FEATURES; Memory size revised. 2.00 Apr 21, 2003 8 Memory size; Flash memory size revised. Fig.8; ROM size revised. 9 Table 2; ROM size revised. 10 ...
Page 121
REVISION HISTORY Rev. Date Page Information about 36PJW-A package version added. 2.03 Feb 10, 2004 Table 12 Fig.100, Fig.101: td(CNVss-port) → th(CNVss-port) 91 Table 17 Table ...
Page 122
REVISION HISTORY Rev. Date Page 1 ROM size of Flash memory version revised. 3.00 Jun 01, 2005 2 Fig.1 M37542F8GP → M37542FxGP Fig.2 M37542F8FP → M37542FxFP 3 Fig.3 M37542F8SP → M37542FxSP 5 Table 1 Performance overview added. 10 Table 2 ...
Page 123
REVISION HISTORY Rev. Date Page 12 Table 3 : ROM size revised and note 2 added. 3.02 Oct 31, 2006 17 ROM : Description added. Fig Note 2 added. 24 Table 57, 132 Notes on ...
Page 124
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...