SCF5250LAG100 Freescale Semiconductor, SCF5250LAG100 Datasheet - Page 32

• Manufacturer Part Number: SCF5250LAG100
• Description: IC MPU COLDFIRE 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: SCF52xxr

Specifications of SCF5250LAG100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, I²C, IDE, MMC, SPI, UART/USART
• Peripherals: DMA, I²S, POR, Serial Audio, WDT
• Number Of I /o: 57
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 144-LQFP
• Eeprom Size: -
• Program Memory Size: -

1
2
3
Figure 9
timing parameters.
32
SCL and SDA are internally synchronized. This setup time must be met only if recognition on a particular clock is required.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and
pull-up resistor values.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are actively being driven or held low by the processor.
M10
M12
M13
Num
M11
1
2
3
provides the I2C-bus and system clock timing diagram and
SCL, SDA Valid to BCLK (input setup)
BCLK to SCL, SDA Invalid (input hold)
BCLK to SCL, SDA Low (output valid)
BCLK to SCL, SDA Invalid (output hold)
Figure 9. I2C and System Clock Timing Relationship
SCL, SDA OUT
SCL, SDA OUT
SCL, SDA IN
SCF5250 Data Sheet:
Table 28. I2C Output Bus Timings
BCLK
Characteristic
Technical
M10
Data,
M11
M12
Rev. 1.3
Table 28
M13
provides the I2C-bus output
Min
4.5
2
–
3
96 MHz
Freescale Semiconductor
Max
10
–
–
–
Units
ns
ns
ns
ns