MC908GR60ACFAE Freescale Semiconductor, MC908GR60ACFAE Datasheet - Page 39

• Manufacturer Part Number: MC908GR60ACFAE
• Description: IC MCU 60K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
$FFFF
$FF80
$FF81
$FF88
Addr.
1. Non-volatile FLASH register
FLASH-1 Control Register
FLASH-1 Block Protect
FLASH-2 Block Protect
Register Name
Register (FL1BPR) (1)
Register (FL2BPR) (1)
COP Control Register
Vector Priority
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Lowest
See page 43.
See page 51.
See page 42.
See page 95.
(COPCTL)
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
(FL1CR)
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Vector
IF24
IF23
IF22
IF21
IF20
IF17
IF16
IF15
↓
BPR7
BPR7
Bit 7
0
0
Table 2-1. Vector Addresses
Address
$FFCC
$FFCD
$FFDC
$FFDD
$FFCE
$FFCF
$FFD0
$FFD1
$FFD2
$FFD3
$FFD4
$FFDB
$FFDE
$FFDF
= Unimplemented
↓
BPR6
BPR6
6
0
0
TIM2 Channel 5 Vector (High)
TIM2 Channel 5 Vector (Low)
TIM2 Channel 4 Vector (High)
TIM2 Channel 4 Vector (Low)
TIM2 Channel 3 Vector (High)
TIM2 Channel 3 Vector (Low)
TIM2 Channel 2 Vector (High)
TIM2 Channel 2 Vector (Low)
Reserved
Timebase Vector (High)
Timebase Vector (Low)
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
.
BPR5
BPR5
5
0
0
Writing clears COP counter (any value)
R = Reserved
Low byte of reset vector
Unaffected by reset
Unaffected by reset
Unaffected by reset
BPR4
BPR4
4
0
0
Vector
HVEN
BPR3
BPR3
Continued on next page
3
0
U = Unaffected
MASS
BPR2
BPR2
Input/Output (I/O) Section
2
0
ERASE
BPR1
BPR1
1
0
BPR0
BPR0
PGM
Bit 0
0
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