MC908GR60ACFAE Freescale Semiconductor, MC908GR60ACFAE Datasheet - Page 188

• Manufacturer Part Number: MC908GR60ACFAE
• Description: IC MCU 60K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
14.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG1
register is cleared. The SIM actively pulls down the RST pin for all internal reset sources.
The COP module is disabled if the RST pin or the IRQ pin is held at V
mode. During a break state, V
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A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set.
CGMXCLK
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
RST
IAB
Reset Recovery Type
TST
Figure 14-6. Sources of Internal Reset
All others
POR/LVI
ILLEGAL ADDRESS RST
RST PULLED LOW BY MCU
ILLEGAL OPCODE RST
Figure 14-5. Internal Reset Timing
on the RST pin disables the COP module.
32 CYCLES
Table 14-2. Reset Recovery
MODRST
COPRST
POR
LVI
Actual Number of Cycles
32 CYCLES
4163 (4096 + 64 + 3)
INTERNAL RESET
67 (64 + 3)
TST
while the MCU is in monitor
VECTOR HIGH
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