MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 202

• Manufacturer Part Number: MCHC908JW32FC
• Description: IC MCU 32K FLASH 8MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FC

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-QFN
• Controller Family/series: HC08
• No. Of I/o's: 29
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI, USB
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Low-Voltage Inhibit (LVI)
17.3.1 Low V
The low V
below the trip voltage, V
CONFIG1 register.
17.3.2 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
17.3.3 Forced Reset Operation
In applications that require V
module to reset the MCU when V
and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
17.3.4 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
continually entering and exiting reset if V
V
202
DD
TRIPF1
rises above the rising trip point voltage, V
by the hysteresis voltage, V
DD
DETECTOR
detector circuit monitors the V
LOW V
DD
V
DD
Detector
DD
TRIPF1
V
V
FROM CONFIG1
DD
DD
DD
> V
≤ V
LVIPWRD
. The V
Figure 17-2. LVI Module Block Diagram
TRIPR1
TRIPF1
to remain above the V
DD
DD
falls below the V
MC68HC908JW32 Data Sheet, Rev. 6
HYS
= 1
= 0
DD
levels below the V
DD
.
DD
LVI circuit can be disabled by the setting the LVIPWRD bit in
fall below V
DD
is approximately equal to V
TRIPR1
voltage and forces a LVI reset when the V
STOP INSTRUCTION
TRIPF1
. This prevents a condition in which the MCU is
TRIPF1
TRIPF1
TRIPF1
level. In the CONFIG1 register, the LVIPWRD
), the LVI will maintain a reset condition until
TO LVISR
level, enabling LVI resets allows the LVI
FROM CONFIG1
LVIOUT
level, software can monitor V
LVIRSTD
FROM CONFIG1
LVISTOP
TRIPF1
. V
TRIPR1
LVI RESET
Freescale Semiconductor
is greater than
DD
DD
voltage falls
by polling