MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 155

• Manufacturer Part Number: MCHC908JW32FC
• Description: IC MCU 32K FLASH 8MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FC

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-QFN
• Controller Family/series: HC08
• No. Of I/o's: 29
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI, USB
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.5.1 USB Control Register (USBCR)
USBEN — USB Module Enable
USBCLKEN — USB Clock Enable
TCxIE — Transfer complete interrupt enable for endpoint x
RESUME — Force RESUME condition
Freescale Semiconductor
This read/write bit enables the USB module. Setting this bit updates the endpoint configuration
according to the definition defined in UEPxCSR, UINTFCR, UEP12BPR and UEP34BPR registers.
User must ensure the 48MHz clock source is ready before the module is enabled. When the USBEN
bit is returned to zero, the module is reset and the device is returned to power state. User is
recommended to reset all the status flags by software before enabling USBEN again. Reset clears this
bit.
This read/write bit enables the 48MHz clock source to the USB module. User must ensure this bit is
set before setting USBEN bit. In USB suspend mode it is recommended to clear this bit for power
saving. Reset clears this bit.
The read/write bit enables CPU interrupt when transfer complete flag (TFRC) of corresponding
endpoint is set. TC0IE is controlling both TFRC0_IN and TFRC0_OUT at the same time. Reset clears
this bit.
This write-only bit forces a resume state (K or non-idle state) onto the USB bus data lines to initiate a
remote wakeup. This bit generates RESUME only if the device is in SUSPEND mode and the remote
wake up feature is enabled by the SET_FEATURE command. The USB control logic ensures the
forced resume duration is greater than 3ms. Reading this bit always returns zero. Writing zero to the
bit has no effect.
1 = USB module enabled
0 = USB module disabled
1 = USB clock enabled
0 = USB clock disabled
1 = Transfer complete interrupt enabled
0 = Transfer complete interrupt disabled
1 = Generates forced RESUME condition on the USB data lines
0 = Default value
Address:
Reset:
Read:
Write:
USBEN
$0051
Bit 7
0
USBCLK-
EN
Figure 11-3. USB Control Register
6
0
MC68HC908JW32 Data Sheet, Rev. 6
TC4IE
5
0
TC3IE
4
0
TC2IE
3
0
TFC1IE
2
0
TC0IE
1
0
USB Module Registers
RESUME
Bit 0
0
0
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