MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 175
![IC MCU 32K FLASH 8MHZ 48-QFN](/photos/12/17/121792/mchc908jw32fc_sml.jpg)
MCHC908JW32FC
Manufacturer Part Number
MCHC908JW32FC
Description
IC MCU 32K FLASH 8MHZ 48-QFN
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.RD3152MMA7260Q.pdf
(232 pages)
Specifications of MCHC908JW32FC
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-QFN
Controller Family/series
HC08
No. Of I/o's
29
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SPI, USB
Rohs Compliant
Yes
Processor Series
HC08JW
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USB
Number Of Programmable I/os
29
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
13.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
DDRC[3:0] — Data Direction Register C Bits
Figure 13-10
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port C data direction. Reset clears DDRC[3:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
DDRC
shows the port C I/O logic.
Address:
Bit
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 3.
0
1
Reset:
Read:
Write:
READ DDRC ($0007)
WRITE DDRC ($0007)
WRITE PTC ($0002)
READ PTC ($0002)
$0006
Bit 7
PTC Bit
0
X
X
(1)
Figure 13-9. Data Direction Register C (DDRC)
= Unimplemented
6
0
Table 13-5. Port C Pin Functions
RESET
I/O Pin Mode
Figure 13-10. Port C I/O Circuit
Input, Hi-Z
MC68HC908JW32 Data Sheet, Rev. 6
Output
5
0
(2)
Table 13-5
NOTE
DDRCx
PTCx
Accesses to DDRC
4
0
Read/Write
DDRC[3:0]
DDRC[3:0]
summarizes the operation of the port C pins.
DDRC3
3
0
DDRC2
2
0
PTC[3:0]
Read
Pin
Accesses to PTC
DDRC1
1
0
PTC[3:0]
PTC[3:0]
DDRC0
Write
Bit 0
PTCx
0
(3)
Port C
175
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