MC9S08DV60ACLC Freescale Semiconductor, MC9S08DV60ACLC Datasheet - Page 109
![IC MCU 60K FLASH 3K RAM 32-LQFP](/photos/12/17/121791/mc9s08dv60aclc_sml.jpg)
MC9S08DV60ACLC
Manufacturer Part Number
MC9S08DV60ACLC
Description
IC MCU 60K FLASH 3K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60ACLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 10 channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60ACLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.5.7
Port G is controlled by the registers listed below.
6.5.7.1
6.5.7.2
Freescale Semiconductor
PTGDD[5:0]
PTGD[5:0]
Reset:
Reset:
Field
Field
5:0
5:0
W
W
R
R
Port G Registers
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
Port G Data Register (PTGD)
0
0
Port G Data Direction Register (PTGDD)
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 6-43. Port G Data Direction Register (PTGDD)
Table 6-41. PTGDD Register Field Descriptions
Table 6-40. PTGD Register Field Descriptions
Figure 6-42. Port G Data Register (PTGD)
PTGDD5
PTGD5
MC9S08DV60 Series Data Sheet, Rev 3
0
0
5
5
PTGDD4
PTGD4
0
0
4
4
Description
Description
PTGDD3
PTGD3
3
0
3
0
PTGDD2
PTGD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTGDD1
PTGD1
0
0
1
1
PTGDD0
PTGD0
0
0
0
0
109
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