MC9S08DV60ACLC Freescale Semiconductor, MC9S08DV60ACLC Datasheet - Page 107
![IC MCU 60K FLASH 3K RAM 32-LQFP](/photos/12/17/121791/mc9s08dv60aclc_sml.jpg)
MC9S08DV60ACLC
Manufacturer Part Number
MC9S08DV60ACLC
Description
IC MCU 60K FLASH 3K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60ACLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 10 channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60ACLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.5.6.3
6.5.6.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
Freescale Semiconductor
PTFPE[7:0]
PTFSE[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
rate control to the desired value to ensure correct operation.
W
W
R
R
PTFPE7
PTFSE7
Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port F bit n.
1 Internal pull-up device enabled for port F bit n.
Output Slew Rate Enable for Port F Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
Port F Pull Enable Register (PTFPE)
0
Port F Slew Rate Enable Register (PTFSE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
PTFPE6
PTFSE6
Figure 6-39. Internal Pull Enable for Port F Register (PTFPE)
Figure 6-40. Slew Rate Enable for Port F Register (PTFSE)
0
0
6
6
Table 6-37. PTFPE Register Field Descriptions
Table 6-38. PTFSE Register Field Descriptions
PTFPE5
PTFSE5
MC9S08DV60 Series Data Sheet, Rev 3
0
0
5
5
PTFPE4
PTFSE4
NOTE
0
0
4
4
Description
Description
PTFPE3
PTFSE3
3
0
3
0
PTFPE2
PTFSE2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTFPE1
PTFSE1
0
0
1
1
PTFPE0
PTFSE0
0
0
0
0
107
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