MCF51QE128CLH Freescale Semiconductor, MCF51QE128CLH Datasheet - Page 24

IC MCU 32BIT 128K FLASH 64-LQFP

MCF51QE128CLH

Manufacturer Part Number
MCF51QE128CLH
Description
IC MCU 32BIT 128K FLASH 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51QEr
Datasheets

Specifications of MCF51QE128CLH

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 20x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
MCF51QE
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
50.33 MHz
Number Of Programmable I/os
54
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
EVBQE128, DEMOQE128
Minimum Operating Temperature
- 40 C
On-chip Adc
20-ch x 12-bit
For Use With
EVBQE128 - BOARD EVAL FLEXIS QE128 FAMILYDEMOQE128 - DEMO BOARD FOR QE128 FLEXIS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF51QE128CLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF51QE128CLH
Quantity:
226
Electrical Characteristics
3.10.3
Table 15
24
No.
and
10
12
11
1
2
3
4
5
6
7
8
9
Figure 18
SPI Timing
C
D
D
D
D
D
D
D
D Slave access time
D Slave MISO disable time
D
D
D
D
Operating frequency
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time
Fall time
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Input
Output
Input
Output
through
Figure 21
Function
MCF51QE128 Series Data Sheet, Rev. 7
describe the timing requirements for the SPI system.
Table 15. SPI Timing
t
Symbol
WSPSCK
t
SPSCK
t
t
Lead
t
t
t
t
t
f
Lag
t
t
t
HO
RO
SU
dis
FO
op
t
t
HI
RI
FI
a
v
f
t
t
Bus
cyc
cyc
Min
1/2
1/2
15
15
25
/2048
0
2
4
1
1
0
0
0
– 30
– 30
1024 t
t
t
cyc
cyc
f
f
2048
Max
Bus
Bus
25
25
25
25
1
1
– 25
– 25
/2
/4
Freescale Semiconductor
cyc
t
t
SPSCK
SPSCK
Unit
t
t
t
t
t
t
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc

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