MC9S08AC8CFGE Freescale Semiconductor, MC9S08AC8CFGE Datasheet - Page 267

• Manufacturer Part Number: MC9S08AC8CFGE
• Description: IC MCU 8BIT 8K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC8CFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 700 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.7.2
Several sources of error exist for A/D conversions. These are discussed in the following sections.
14.7.2.1
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R
below 5 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
14.7.2.2
Leakage on the I/O pins can cause conversion error if the external analog source resistance (R
If this error cannot be tolerated by the application, keep R
1/4
14.7.2.3
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
Freescale Semiconductor
LSB
•
•
•
•
•
•
•
leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode).
There is a 0.1 μF low-ESR capacitor from V
There is a 0.1 μF low-ESR capacitor from V
If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
V
V
Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to the ADC1SC1 with a
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V
There is no I/O switching, input or output, on the MCU during the conversion.
Place a 0.01 μF capacitor (C
improve noise issues but will affect sample rate based on the external analog source resistance).
DDAD
SSAD
WAIT instruction or STOP instruction.
noise but increases effective conversion time due to stop recovery.
Sources of Error
DD
LSB
Sampling Error
Pin Leakage Error
Noise-Induced Errors
(and V
noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
to V
(at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
SSAD
REFL
.
, if connected) is connected to V
MC9S08AC16 Series Data Sheet, Rev. 8
AS
) on the selected input channel to V
REFH
DDAD
AS
to V
to V
SS
lower than V
at a quiet point in the ground plane.
REFL
SSAD
.
.
Analog-to-Digital Converter (S08ADC10V1)
DDAD
REFL
/ (2
or V
N
*I
SSAD
LEAK
(this will
) for less than
AS
AS
) is kept
) is high.
DD
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