EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 87
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 23. Intel Bus Mode Read States—Multiplexed Address and Data Bus
Table 24. Intel Bus Mode Write States—Multiplexed Address and Data Bus
PS019215-0910
STATE T1
STATE T2
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
The Read cycle begins in State T1. The CPU drives the address onto the DATA bus and the
associated chip select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
During State T2, the CPU removes the address from the DATA bus and asserts the RD
signal. Depending upon the instruction, either the MREQ or IORQ signal is asserted.
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel™ bus mode cycle.
The Write cycle begins in State T1. The CPU drives the address onto the DATA bus and
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
During State T2, the CPU removes the address from the DATA bus and drives the Write
data onto the DATA bus. The WR signal is asserted to indicate a Write operation.
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write
operation. The CPU holds the data and address buses through the end of T4. The bus cycle
is completed at the end of T4.
WAIT
WAIT
Intel™ Bus Mode—Multiplexed Address and Data Bus
During Read operations with multiplexed address and data, the Intel™ bus mode employs
four states—T1, T2, T3, and T4 as listed in
During Write operations with multiplexed address and data, the Intel™ bus mode employs
four states—T1, T2, T3, and T4 as listed in
Signal timing for Intel bus mode with multiplexed address and data is displayed for a Read
operation in
Figure 15
clock cycles in duration.
assertion of one wait state (T
) are asserted until the READY pin is driven High.
) are asserted until the READY pin is driven High.
on page 79 and
Figure 15
on page 79 and for a Write operation in
Figure 15
Figure 16
WAIT
) by the selected peripheral.
on page 79 and
on page 80, each Intel bus mode state is 2 CPU system
Table
Table
23.
24.
Figure 16
on page 80 also display the
Figure 16
Chip Selects and Wait States
Product Specification
on page 80. In
eZ80F91 MCU
78
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