EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 317
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 192. EMAC Non-Back-To-Back IPG Register—Part 1
PS019215-0910
Bit
Position
7
[6:0]
IPGT
Bit
Reset
CPU Access
Note: R/W = Read/Write
Bit
Position
7
[6:0]
IPGR 1
EMAC Non-Back-To-Back IPG Register—Part 1
Part 1 of the EMAC non-back-to-back IPG Register is a programmable field representing
the optional carrier sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier Deference. If
a carrier is detected during the timing of IPGR1, the EMAC defers to the carrier. If, how-
ever, the carrier becomes active after IPGR1, the EMAC continues timing for IPGR2 and
transmits, knowingly causing a collision. This collision acts to ensure fair access to the
medium. Its range of values is
represents the Carrier Sense Window Referencing depicted tin IEEE 802.3, Section
4.2.3.2.1.
EMAC Non-Back-To-Back IPG Register—Part 2
Part 2 of the EMAC non-back-to-back IPG Register is a programmable field representing
the non-back-to-back IPG. Its default is
0.96 µs at 100 Mbps or 9.6 µs at 10 Mbps. See
Value
0
00h–7Fh The number of bytes of IPG.
Value
0
00h–
7Fh
Description
Reserved.
This is a programmable field representing the optional carrier
sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier
Deference.
R/W
Description
Reserved.
7
0
R/W
6
0
R/W
5
0
00h
R/W
to IPGR2. See
4
0
12h
R/W
, which represents the minimum IPG of
3
1
Table 193
Table
R/W
(EMAC_IPGR1 = 002Eh)
2
1
192. The default setting of 0Ch
on page 309.
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
308
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