EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 54
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
- Current page: 54 of 384
- Download datasheet (3Mb)
Low-Power Modes
PS019215-0910
SLEEP Mode
HALT Mode
The eZ80F91 device provides a range of power-saving features. The highest level of
power reduction is provided by SLEEP mode with all peripherals disabled, including
VBO. The next level of power reduction is provided by the HALT instruction. The most
basic level of power reduction is provided by the clock peripheral power-down registers.
Execution of the CPU’s SLP instruction puts the eZ80F91 device into SLEEP mode. In
SLEEP mode, the operating characteristics are:
•
•
•
•
•
The CPU is brought out of SLEEP mode by any of the following operations:
•
•
•
•
•
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. For more information, see
Execution of the CPU’s HALT instruction puts the eZ80F91 device into HALT mode.
In HALT mode, the operating characteristics are:
•
•
•
The primary crystal oscillator is disabled.
The system clock is disabled.
The CPU is idle.
The Program Counter (PC) stops incrementing.
The 32 kHz crystal oscillator continues to operate and drives the real-time clock and
WDT (if WDT is configured to operate from the 32 kHz oscillator).
A RESET via the external RESET pin driven Low.
A RESET via a real-time clock alarm.
A RESET via a WDT time-out (if running out of the 32 kHz oscillator and configured
to generate a RESET on time-out).
A RESET via execution of a Debug RESET command.
A RESET via the Low-Voltage Brownout (VBO) detection circuit, if enabled.
The primary crystal oscillator is enabled and continues to operate.
The system clock is enabled and continues to operate.
The CPU is idle.
Figure 4
on page 43.
Product Specification
Low-Power Modes
45
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