EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 264
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 148. ZDI Bus Control Register
Address Space)
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_BUSAcK_En
6
ZDI_BUS_STAT
[5:0]
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the eZ80F91 device
fetches the data from the memory address currently pointed to by the Program
Counter, PC; the Program Counter is then incremented. In Z80
memory address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the memory
address is PC[23:0]. For more information on Z80 and ADL MEMORY modes, refer
to the eZ80
gram Counter, PC, increments after each data Read. However, the ZDI register address
does not increment automatically when this register is accessed. As a result, the ZDI
master reads any number of data bytes out of memory via the ZDI Read Memory reg-
ister. See
Value
0
1
0
1
000000
Table 149
®
R
7
0
CPU User Manual (UM0077) available on www.zilog.com. The Pro-
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
R
6
0
on page 256.
(ZDI_BUS_STAT = 17h in the ZDI Register Read Only
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
®
Product Specification
MEMORY mode, the
R
0
0
Zilog Debug Interface
eZ80F91 MCU
Table
148.
255
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