Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 350
Z16F3211AL20SG
Manufacturer Part Number
Z16F3211AL20SG
Description
IC ZNEO MCU FLASH 32K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F3211AL20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F3211AL20SG
Manufacturer:
Zilog
Quantity:
557
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Table 181. Oscillator Divide Register (OSCDIV)
BITS
FIELD
RESET
R/W
ADDR
* The reset value is 08H if the option bit LPOPT is 0.
PS022008-0810
Bit Position
[3]
WDFEN
[2]
FLPEN
[1:0]
SCKSEL
Bit Position
[7:0]
DIV
Oscillator Divide Register
00H to FFH
7
Value (H) Description
Value (H)
The Oscillator Divide register (OSCDIV) provides the value to divide the system clock by.
The Oscillator Divide register must be unlocked before writing. Writing the two-step
sequence
The register locks after completion of a register write to the OSCDIV.
00
01
10
11
0
1
0
1
E7H
6
Oscillator Divide
00H - divider is disabled, all other entries are the divide value for scaling the
system clock.
Description
WDT Oscillator Failure Detection Enable
Failure detection of WDT oscillator is disabled.This bit is
automatically if a WDT oscillator failure is detected.
Failure detection of WDT oscillator is enabled.
Flash Low Power Mode Enable
Flash Low Power Mode is disabled.
Flash Low Power Mode is enabl ed. The Flash will be powered down during
idle periods of the clock and powered up during Flash reads. This bit must
only be set if the frequency of the primary oscillator source is 8 MHz or lower.
The reset value of this bit is controlled by the LPOPT option bit during reset.
System Clock Oscillator Select
Internal precision oscillator functions as system clock at 5.6 MHz.
Crystal oscillator or external clock driver functions as system clock.
Reserved.
Watchdog Timer oscillator functions as system clock.
followed by
5
P R E L I M I N A R Y
18H
to the Oscillator Control register address unlocks it.
4
FF_E0A1H
00H*
R/W
DIV
3
2
Product Specification
ZNEO
1
Oscillator Control
Z16F Series
cleared
0
334
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