Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 265
Z16F3211AL20SG
Manufacturer Part Number
Z16F3211AL20SG
Description
IC ZNEO MCU FLASH 32K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F3211AL20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F3211AL20SG
Manufacturer:
Zilog
Quantity:
557
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Table 124. ADC0 Data Low Bits Register (ADC0D_L)
Table 125. Sample and Settling Time (ADCSST)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position Value (H) Description
[7:6]
[5:0]
Reserved
ADC0 Data Low Bits Register
Sample Settling Time Register
7
7
0
The ADC0 Data Low Bits register contains the lower bits of the ADC0 output. Access to
the ADC0 Data Low Bits register is Read-Only.
The sample settling time register is used to program the length of time from the SAMPLE/
HOLD signal to the START signal, when the conversion begins. The number of clock
cycles required for settling varies from system to system depending on the system clock
period used. You must program this register to contain the number of clocks required to
meet a 0.5 S minimum settling time.
00–11b
ADC0D_L
0
X
R
Reserved
ADC0 Low Bits
These bits are the 2 least significant bits of the 10-bit ADC0 output. These bits
are undefined after a Reset.
Reserved—Must Be 0.
R
6
6
0
5
5
0
P R E L I M I N A R Y
4
4
1
FF-E503H
FF-E504H
3
3
1
Reserved
X
R
SST
R/W
2
2
1
Product Specification
ZNEO
1
1
1
Analog Functions
Z16F Series
0
0
1
249
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