Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 131
Z16F3211AL20SG
Manufacturer Part Number
Z16F3211AL20SG
Description
IC ZNEO MCU FLASH 32K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F3211AL20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F3211AL20SG
Manufacturer:
Zilog
Quantity:
557
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PS022008-0810
PWM Reload Event
PWM Prescaler
PWM Period and Count Resolution
PWM Output Polarity and Off-State
The default off-state and polarity of the PWM outputs are controlled by the option bits
PWMHI and PWMLO. The PWMHI option controls the off-state and polarity for PWM
high-side outputs PWMH0, PWMH1, and PWMH2. The PWMLO option controls the
off-state and polarity for low-side outputs PWML0, PWML1, and PWML2.
The off-state is the value programmed in the option bit. For example, programming
to 1 makes the off-state of PWMH0, PWMH1, and PWMH2 a High logic value and the
active state a Low logic value. Conversely, programming PWMHI to 0 causes the off-state
to be a Low logic value. PWMLO is programmed in a similar manner.
PWM Enable
The MCEN option bit enables output pairs PWM0, PWM1, and PWM2. If the Motor
Control option is not enabled, the PWM outputs remain in a high-impedance state after
reset and is used as alternate functions like general purpose input. If the Motor Control
option is enabled, following a Power-On Reset (POR) the PWM pins enter a high
impedance state. As the internal reset proceeds, the PWM outputs are forced to the off-
state as determined by the PWMHI and PWMLO off-state option bits.
To prevent erroneous PWM pulse-widths and periods, registers that control the timing of
the output are buffered. Buffering causes all the PWM compare values to update. In other
words, the registers controlling the duty cycle, and clock source prescaler only take effect
on a PWM reload event. A PWM reload event is configured to occur at the end of each
PWM period or only every 2, 4, or 8 PWM periods by setting the RELFREQ bits in the
PWM Control 1 Register
by setting the READY bit in the
READY bit is set to 1, the buffered values take effect at the next reload event.
The prescaler decreases the PWM clock signal by factors of 1, 2, 4, or 8 with respect to the
system clock. The PRES[1:0] bit field in the
controls prescaler operation. This 2-bit PRES field is buffered so that the prescale value
only changes on a PWM Reload event.
The PWM counter operates in two modes to allow edge-aligned and center-aligned
outputs.
outputs. The mode in which the PWM operates determine the period of the PWM outputs
Figure 21
and
Figure 22
(PWMCTL1). Software indicates that all new values are ready
P R E L I M I N A R Y
PWM Control 0 Register (PWMCTL0)
on page 117 illustrate edge and center-aligned PWM
PWM Control 1 Register (PWMCTL1)
Multi-Channel PWM Timer
Product Specification
ZNEO
to 1. When the
Z16F Series
PWMHI
116
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