Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 101
Z16F3211AL20SG
Manufacturer Part Number
Z16F3211AL20SG
Description
IC ZNEO MCU FLASH 32K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F3211AL20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F3211AL20SG
Manufacturer:
Zilog
Quantity:
557
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Table 43. Last IRQ Register (LASTIRQ)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
Last IRQ Register
Interrupt Request 0 Register
Always 0
R
7
0
Reserved—These bits are reserved
WDTOSC—WDT Oscillator Fail
If this bit is 1, a WDT oscillator fail exception occurred. Writing 1 to this bit clears it to 0.
PRIOSC—Primary Oscillator Fail
If this bit is 1, a primary oscillator fail exception occurred. Writing 1 to this bit clears it
to 0.
WDT—Watchdog Timer Interrupt
If this bit is 1, a WDT exception occurred. Writing 1 to this bit clears it to 0.
When an interrupt occurs, the 5th bit value of the interrupt vector is stored in the register.
This register allows the software to determine which interrupt source was last serviced.
It is used by RTOS which have a single interrupt entry point. To implement this the
software must set all interrupt vectors to the entry point address. The entry point service
routine then reads this register to determine which source caused the interrupt or exception
and respond accordingly.
The interrupt request 0 (IRQ0) register (see
requests for both vectored and polled interrupts. When a request is presented to the
interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are
globally enabled (vectored interrupts), the interrupt controller passes an interrupt request
to the ZNEO CPU. If interrupts are globally disabled (polled interrupts), the ZNEO CPU
reads the interrupt request 0 register to determine if any interrupt requests are pending.
Writing 1 to the bits in this register clears the interrupt. The bits of this register are set by
writing 1 to the interrupt request 0 set regsiter (IRQ0SET) at address FF_E031H.
R/W
6
0
R/W
5
0
P R E L I M I N A R Y
IRQADR
R/W
4
0
FF_E023H
Table 44
R/W
3
0
on page 87) stores the interrupt
R/W
2
1
Product Specification
ZNEO
Interrupt Controller
R
1
0
Always 00
Z16F Series
R
0
0
86
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