ST72F63BD6U1TR STMicroelectronics, ST72F63BD6U1TR Datasheet - Page 95
![MCU 8BIT LS USB 32KB FLSH 40-QFN](/photos/12/14/121423/497-40-qfn_series_sml.jpg)
ST72F63BD6U1TR
Manufacturer Part Number
ST72F63BD6U1TR
Description
MCU 8BIT LS USB 32KB FLSH 40-QFN
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BD6U1TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-QFN
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5623
497-5623-2
497-5623
ST72F63BD6U1
497-5623-2
497-5623
ST72F63BD6U1
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ST7263Bxx
Baud Rate register (SCIBRR)
Reset value: 0000 0000 (00h)
Table 29.
Table 30.
Table 31.
.
SCP1
7
TR dividing factor
RR dividing factor
[7:6] SCP[1:0] First SCI Prescaler
[5:3] SCT[2:0] SCI Transmitter rate divisor
[2:0] SCR[2:0] SCI Receiver rate divisor.
Prescaling factors
TR dividing factors
RR dividing factor
SCP0
PR prescaling factor
These 2 prescaling bits allow several standard clock division ranges (see
Table
These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division
applied to the bus clock to yield the transmit rate clock (see
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied
to the bus clock to yield the receive rate clock (see
128
16
32
64
1
2
4
8
1
2
4
29).
13
1
3
4
SCT2
Doc ID 7516 Rev 8
SCT1
Read/write
SCT2
SCR2
0
0
0
0
1
1
1
1
0
0
0
SCT0
SCP1
SCR2
0
0
1
1
SCT1
SCR1
Table
0
0
1
1
0
0
1
1
0
0
1
31).
On-chip peripherals
Table
SCR1
30).
SCP0
SCT0
SCR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SCR0
0
95/186
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