ST72F63BD6U1TR STMicroelectronics, ST72F63BD6U1TR Datasheet - Page 50
![MCU 8BIT LS USB 32KB FLSH 40-QFN](/photos/12/14/121423/497-40-qfn_series_sml.jpg)
ST72F63BD6U1TR
Manufacturer Part Number
ST72F63BD6U1TR
Description
MCU 8BIT LS USB 32KB FLSH 40-QFN
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BD6U1TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-QFN
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5623
497-5623-2
497-5623
ST72F63BD6U1
497-5623-2
497-5623
ST72F63BD6U1
Available stocks
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- Download datasheet (3Mb)
I/O ports
9.3.4
Table 15.
1. Reset state
9.3.5
Note:
Note:
50/186
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Port D
Port D
Port D description
Register description
DATA registers (PxDR)
Address
Reset value
For Port C, unused bits (7-3) are not accessible.
The DR register has a specific behavior according to the selected input/output configuration.
Writing the DR register is always taken into account even if the pin is configured as an input.
Reading the DR register returns either the DR register latch content (pin configured as
output) or the digital value applied to the I/O pin (pin configured as input).
When using open-drain I/Os in output configuration, the value read in DR is the digital value
applied to the I/Opin.
without pull-up
without pull-up
without pull-up
without pull-up
with pull-up
with pull-up
with pull-up
with pull-up
Port A Data register (PADR): 0000h
Port B Data register (PBDR): 0002h
Port C Data register (PCDR): 0004h
Port D Data register (PDDR): 0006h
Port A: 0000 0000 (00h)
Port B: 0000 0000 (00h)
Port C: 1111 x000 (FXh)
Port D: 0000 0000 (00h)
Input
(1)
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
I / O
Output
Doc ID 7516 Rev 8
Analog input (ADC)
Analog input (ADC)
Analog input (ADC)
Analog input (ADC)
Signal
Alternate function
CH[3:0] = 1000
(ADCCSR)
CH[3:0] = 1001
(ADCCSR)
CH[3:0] = 1010
(ADCCSR)
CH[3:0] = 1011
(ADCCSR)
Condition
ST7263Bxx
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