ST72F63BD6U1TR STMicroelectronics, ST72F63BD6U1TR Datasheet - Page 181
![MCU 8BIT LS USB 32KB FLSH 40-QFN](/photos/12/14/121423/497-40-qfn_series_sml.jpg)
ST72F63BD6U1TR
Manufacturer Part Number
ST72F63BD6U1TR
Description
MCU 8BIT LS USB 32KB FLSH 40-QFN
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BD6U1TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-QFN
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5623
497-5623-2
497-5623
ST72F63BD6U1
497-5623-2
497-5623
ST72F63BD6U1
Available stocks
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ST7263Bxx
16
16.1
Note:
16.2
16.3
16.4
Known limitations
PA2 limitation with OCMP1 enabled
Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F63Bxxxxx$x7
it has been corrected in Rev W Flash devices (with Internal Sales Type 72F63Bxxxxx$x9
Refer to
When output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.
In particular, PA2 is switched to its alternate function mode, SCL. As a consequence, the
PA2 pin is forced to be floating (steady level of I
(PADDR+PADR) has set it as output low. However, it can be still used as an input or can be
controlled by the I
Unexpected RESET fetch
Description
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
USB behavior with LVD disabled
Description
If the LVD is disabled on 4K and 8K ROM devices (ST7263BK1M1, ST72BK2M1,
ST7263BKB1, ST7263BK2B1 only), the USB is disabled by hardware. The LVD is
consequently forced by ST to ‘0’ (LVD enabled). Refer to the ST7263Bx option list for details.
I
Description
In multimaster configurations, if the ST7 I
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a re-start and Slave address to re-initiate communication
2
C multimaster
Figure 85 on page 183
2
C cell when enabled (where I
2
C, it may ignore the START condition from the other I
Doc ID 7516 Rev 8
2
C receives a START condition from another I
2
2
C clock) even if port configuration
C is available).
Known limitations
2
C master. In
181/186
2
C
)
.
)
;
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