P87C554SFAA,512 NXP Semiconductors, P87C554SFAA,512 Datasheet - Page 47

• Manufacturer Part Number: P87C554SFAA,512
• Description: IC 80C51 MCU 16K OTP 64-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C554SFAA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Cpu Family: 87C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 7-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 68PLCC
• Family Name: 87C
• Maximum Speed: 16 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1255-5; 935263922512; P87C554SFAA

Philips Semiconductors
Table 8.
Table 9.
2003 Jan 28
STATUS
STATUS
STATUS
STATUS
(S1STA)
(S1STA)
(S1STA)
(S1STA)
CODE
CODE
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
A0H
A8H
B0H
B8H
C0H
C8H
A STOP condition or
repeated START
condition has been
received while still
addressed as
SLV/REC or SLV/TRX
SLV/REC or SLV/TRX
Own SLA+R has
been received; ACK
h
has been returned
Arbitration lost in
SLA+R/W as master;
Own SLA+R has
been received, ACK
has been returned
Data byte in S1DAT
has been transmitted;
ACK has been
ACK has been
received
Data byte in S1DAT
has been transmitted;
NOT ACK h
NOT ACK has been
received
Last data byte in
S1DAT has been
transmitted (AA = 0);
ACK has been
received
SIO1 HARDWARE
SIO1 HARDWARE
SIO1 HARDWARE
SIO1 HARDWARE
STATUS OF THE
STATUS OF THE
STATUS OF THE
STATUS OF THE
Slave Receiver Mode (Continued)
Slave Transmitter Mode
di i
I
I
b
2
2
C BUS AND
C BUS AND
i
h
d (AA
b
b
d
0)
No STDAT action or
No STDAT action or
No STDAT action or
No STDAT action
Load data byte or
load data byte
Load data byte or
load data byte
Load data byte or
load data byte
No S1DAT action or
no S1DAT action or
no S1DAT action or
no S1DAT action
No S1DAT action or
no S1DAT action or
no S1DAT action or
no S1DAT action
TO/FROM S1DAT
TO/FROM S1DAT
TO/FROM S1DAT
TO/FROM S1DAT
APPLICATION SOFTWARE RESPONSE
APPLICATION SOFTWARE RESPONSE
STA
STA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
TO S1CON
TO S1CON
STO
STO
2
C, PWM, capture/compare,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
47
SI
SI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
AA
01
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes
free
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1. A START condition
will be transmitted when the bus becomes free.
Last data byte will be transmitted and ACK bit will be
received
Data byte will be transmitted; ACK will be received
Last data byte will be transmitted and ACK bit will be
received
Data byte will be transmitted; ACK bit will be received
Last data byte will be transmitted and ACK bit will be
received
Data byte will be transmitted; ACK bit will be received
Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes
free
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1. A START condition
will be transmitted when the bus becomes free.
Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes
free
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1. A START condition
will be transmitted when the bus becomes free.
NEXT ACTION TAKEN BY SIO1 HARDWARE
NEXT ACTION TAKEN BY SIO1 HARDWARE
80C554/87C554
Product data