LPC2888FET180/01,5 NXP Semiconductors, LPC2888FET180/01,5 Datasheet - Page 19

• Manufacturer Part Number: LPC2888FET180/01,5
• Description: IC ARM7 MCU FLASH 1MB 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2800r

Specifications of LPC2888FET180/01,5

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, UART/USART, USB
• Peripherals: DMA, I²S, LCD, WDT
• Number Of I /o: 85
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC28
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 81
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM10092
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: OM10092 - EVAL BOARD FOR LPC288X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4528

NXP Semiconductors
LPC2880_LPC2888_3
Preliminary data sheet
6.11.1 Features
6.12.1 Features
6.13.1 Features
6.12 Real-time clock
6.13 General purpose DMA controller
The WDT clock increments a 32-bit Prescale Counter, the value of which is continually
compared to the value of the Prescale Register. When the Prescale Counter matches the
Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit
Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the
value in the Prescale Register plus one.
The value of the Timer Counter is continually compared to the values in two registers
called Match Register 0 and 1. When/if the value of the Timer Counter matches that of
Match Register 0 at a WDT clock edge, a signal ‘m0’ can be asserted to the Event Router,
which can be programmed to send an interrupt signal to the Interrupt Controller as a
result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT
clock edge, a signal ‘m1’ can be asserted to the CGU, which resets the chip as a result.
The CGU also includes a flag to indicate whether a reset is due to a watchdog time-out.
The Real-time clock is a set of counters for measuring time when system power is on, and
optionally when it is off. It uses little power in either mode.
The General Purpose DMA controller (GPDMA) is an AMBA AHB compliant master
allowing selected LPC2880/2888 peripherals to have DMA support. Peripherals that can
be serviced by the GPDMA channels include the SD/MCI card interface, UART TX and/or
RX, the I
16-bit dual DACs, the Simple Analog In (SAI) interfaces for data from the I
16-bit dual ADCs, and the LCD interface.
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Optionally resets chip (via Clock Generation Unit) if not periodically reloaded.
Optional interrupt via Event Router.
32-bit Prescaler and 32-bit Counter allow extended watchdog period.
Measures the passage of time to maintain a calendar and clock.
Ultra Low Power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
Dedicated 32 kHz oscillator.
Dedicated power supply pin can be connected to a battery or to the main 1.8 V.
Eight DMA channels. Each channel can support a unidirectional transfer, or a pair of
channels can be used together to follow a linked list of buffer addresses and transfer
counts.
The GPDMA provides 16 peripheral DMA request lines. Most of these are connected
to the peripherals listed above; two can be used for external requests.
2
C-bus interface, the Simple Analog Out (SAO) front-ends to the I
16/32-bit ARM microcontrollers with external memory interface
Rev. 03 — 17 April 2008
LPC2880; LPC2888
© NXP B.V. 2008. All rights reserved.
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S/DAI and
S/DAO and
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