P80C554SFBD,157 NXP Semiconductors, P80C554SFBD,157 Datasheet - Page 22

• Manufacturer Part Number: P80C554SFBD,157
• Description: IC 80C51 MCU 8BIT ROMLESS 64LQFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C554SFBD,157

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 8 MHz, 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2086; 935268881157; P80C554SFBD

generator. Its operation is the same, including the use of timer 1 as a
prescaler and counter are common to both PWM channels. The 8-bit
equal to, or less than the counter value, the output will be HIGH. The
Philips Semiconductors
During the early stages of software development/debugging, the
watchdog may be disabled by tying the EW pin high. At a later
stage, EW may be tied low to complete the debugging process.
Watchdog Software Example: The following example shows how
watchdog operation might be handled in a user program.
;at the program start:
T3
PCON
WATCH-INTV EQU 156
;to be inserted at each watchdog reload location within
;the user program:
LCALL WATCHDOG
;watchdog service routine:
WATCHDOG: ORL PCON,#10H ;set condition flag (PCON.4)
If it is possible for this subroutine to be called in an erroneous state,
then the condition flag WLE should be set at different parts of the
main program.
Serial I/O
The 8xC554 is equipped with two independent serial ports: SIO0
and SIO1. SIO0 is a full duplex UART port and is similar to the
Enhanced UART serial port. SIO1 accommodates the I
SIO0: SIO0 is a full duplex serial I/O port identical to that of the
Enhanced UART except Time 2 cannot be used as a baud rate
baud rate generator.
Port 5 Operation
Port 5 may be used to input up to 8 analog signals to the ADC.
Unused ADC inputs may be used to input digital inputs. These
inputs have an inherent hysteresis to prevent the input logic from
drawing excessive current from the power lines when driven by
analog signals. Channel to channel crosstalk (Ct) should be taken
into consideration when both analog and digital signals are
simultaneously input to Port 5 (see, D.C. characteristics in data
sheet).
Port 5 is not bidirectional and may not be configured as an output
port. All six ports are multifunctional, and their alternate functions
are listed in the Pin Descriptions section of this datasheet.
Pulse Width Modulated Outputs
The 8xC554 contains two pulse width modulated output channels
(see Figure 19). These channels generate pulses of programmable
length and interval. The repetition frequency is defined by an 8-bit
prescaler PWMP, which supplies the clock for the counter. The
counter counts modulo 255, i.e., from 0 to 254 inclusive. The value
of the 8-bit counter is compared to the contents of two registers:
PWM0 and PWM1. Provided the contents of either of these registers
is greater than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers are
pulse-width-ratio is therefore defined by the contents of the registers
PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1
and may be programmed in increments of 1/255.
2003 Jan 28
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
MOV T3,WATCH-INV
RET
EQU 0FFH ;address of watchdog timer T3
EQU 087H ;address of PCON SFR
;watchdog interval (e.g., 100 ms)
;load T3 with watchdog interval
2
C bus.
2
C, PWM, capture/compare,
22
PWM0 (FCH)
PWMn. The PWM outputs may also be configured as a dual DAC. In
reducing internal noise during the conversion. This option is selected
the ADC is active in the idle mode, and with the AIDL bit cleared, the
Buffered PWM outputs may be used to drive DC motors. The
rotation speed of the motor would be proportional to the contents of
this application, the PWM outputs must be integrated using
conventional operational amplifier circuitry. If the resulting output
voltages have to be accurate, external buffers with their own analog
supply should be used to buffer the PWM outputs before they are
integrated. The repetition frequency f
give by:
This gives a repetition frequency range of 246 Hz to 62.8 kHz
(f
to 83.4 Hz. By loading the PWM registers with either 00H or FFH,
the PWM channels will output a constant HIGH or LOW level,
respectively. Since the 8-bit counter counts modulo 255, it can never
actually reach the value of the PWM registers when they are loaded
with FFH.
When a compare register (PWM0 or PWM1) is loaded with a new
value, the associated output is updated immediately. It does not
have to wait until the end of the current counter period. Both PWMn
output pins are driven by push-pull drivers. These pins are not used
for any other purpose.
Prescaler frequency control register PWMP
PWMP.0-7
Reading PWMP gives the current reload value. The actual count of
the prescaler cannot be read.
PWM1 (FDH)
Analog-to-Digital Converter
The analog input circuitry consists of an 8-input analog multiplexer
and a 10-bit, straight binary, successive approximation ADC. The
A/D can also be operated in 8-bit mode with faster conversion times
by setting bit ADC8 (AUXR1.7). The 8-bit results will be contained in
the ADCH register. The analog reference voltage and analog power
supplies are connected via separate input pins. For 10-bit accuracy,
the conversion takes 50 machine cycles, i.e., 18.75 s at an
oscillator frequency of 16 MHz, 12.5 s at an oscillator frequency of
24 MHz. For the 8-bit mode, the conversion takes 24 machine
cycles. Input voltage swing is from 0 V to +5 V. Because the internal
DAC employs a ratiometric potentiometer, there are no
discontinuities in the converter characteristic. Figure 20 shows a
functional diagram of the analog input circuitry.
The ADC has the option of either being powered off in idle mode for
reduced power consumption or being active in idle mode for
by the AIDL bit of AUXR1 register (AUXR1.6). With the AIDL bit set,
ADC is powered off in idle mode.
PWMP (FEH)
OSC
PWM0/1.0-7} Low/high ratio of PWMn +
f
PWM
= 16 MHz). At f
+
(1 ) PWMP)
MSB
MSB
7
Prescaler division factor = PWMP + 1.
7
f
OSC
OSC
6
6
= 24 MHz, the frequency range is 368 Hz
255
5
5
4
4
PWM
, at the PWMn outputs is
3
3
80C554/87C554
255 * (PWMn)
(PWMn)
Reset Value = 00H
Reset Value = 00H
2
2
Product data
1
1
LSB
LSB
0
0