ADUC7024BCPZ62 Analog Devices Inc, ADUC7024BCPZ62 Datasheet - Page 10

• Manufacturer Part Number: ADUC7024BCPZ62
• Description: IC MCU FLSH 62K ANLG I/O 64LFCSP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7024BCPZ62

• Core Size: 16/32-Bit
• Program Memory Size: 62KB (62K x 8)
• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Core Processor: ARM7
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 30
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 30
• Ram Memory Size: 8KB
• Cpu Speed: 44MHz
• No. Of Timers: 4
• Digital Ic Case Style: LFCSP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Package: 64LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 44 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 30
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7019/20/21/22/24/25/26/27/28/29
Table 3. External Memory Read Cycle
Parameter
CLK
t
t
t
t
t
t
t
t
t
t
t
1
MS_AFTER_CLKH
ADDR_AFTER_CLKH
AE_H_AFTER_MS
AE
HOLD_ADDR_AFTER_AE_L
RD_L_AFTER_AE_L
RD_H_AFTER_CLKH
RD
DATA_BEFORE_RD_H
DATA_AFTER_RD_H
RELEASE_MS_AFTER_RD_H
See Table 78.
1
AD[16:1]
ECLK
MSx
BHE
BLE
A16
WS
AE
RS
FFFF
t
MS_AFTER_CLKH
CLK
t
ADDR_AFTER_CLKH
t
AE_H_AFTER_MS
Min
1/MD clock
4
4
0
16
8
2348
t
AE
t
RD_L_AFTER_AE_L
Figure 4. External Memory Read Cycle (See Table 78)
XXXX CDEF XX
t
HOLD_ADDR_AFTER_AE_L
t
RD
Typ
ns typ × (POWCON[2:0] + 1)
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (! XMxPAR[10] ) × CLK
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
(XMxPAR[3:0] + 1) × CLK
+ (! XMxPAR[9]) × CLK
1 × CLK
t
RD_H_AFTER_CLKH
t
DATA_BEFORE_RD_H
t
Rev. C | Page 10 of 96
DATA_AFTER_RD_H
234A
XX
Max
8
16
4
89AB
t
RELEASE_MS_AFTER_RD_H
Unit
ns
ns
ns