AT91SAM9261B-CU Atmel, AT91SAM9261B-CU Datasheet - Page 42

• Manufacturer Part Number: AT91SAM9261B-CU
• Description: MCU ARM9 ULTRA LOW PWR 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 240MHz
• Total Internal Ram Size: 160KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/3.3V
• Operating Supply Voltage (max): 1.32/1.95/3.6V
• Operating Supply Voltage (min): 1.08/1.65/2.7/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 217
• Package Type: LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 160 KB
• Interface Type: JTAG,SPI, SSC, TWI, UART
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 96
• Ram Memory Size: 160KB
• Cpu Speed: 190MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Table 13-1.
42
Doc.
Rev.
6062DS
6062ES
6062FS
6062GS
6062HS
6062IS
6062JS
AT91SAM9261 Preliminary
Source
2292
2946
2475
2474
2480
3068
3147
3067
3503
3660, 3695
3660
3491
5042
5027
rfo
4965
4844
4835
4241
5250
5248
Revision History (Continued)
Comments
Corrected MIPS and speed on page 1.
Added information on EBI NCS0 hwhen BMS = 0 in
Updated information on JTAGSEL in
Section 6.1 “JTAG Port Pins” on page
Reformatted
Mapping,” on page 16
Removed information on Timer Counter clock assignments in
37.
Inserted new
Changed pin name for ball D9 to SHDN in
Package
Updated information on shutdown pin in
Updated peripheral mnemonics in
Added note to
Updated VDDOSC, VDDPLL and VDDIOM ranges in”Features”,
Peripheral,” on page 5
Added ROM to
Updated
Controller Block Diagram,” on page
Added
Table 10-4, “Multiplexing on PIO Controller C,” on page
PCO - PC7 and PC12-PC13 power supplies are VDDIOP not VDDIOM.
Table 10-2, “Multiplexing on PIO Controller A,” on page 31
PA30-PA31 power supplies are VDDIOP not VDDIOM
Section 8.1.2 “Boot
Section 8.1.2.1 “BMS = 1, Boot on Embedded
Section 5.1 “Power
Table 10-3, “Multiplexing on PIO Controller B,” on page
Figure 9-3, “Power Management Controller Block Diagram,” on page
controller representation, the divider has been updated.
Table 4-1 on page
PCO - PC7, PC8 - PC11, PC12 - PC15 power supplies are VDDIOP not VDDIOM.
Section 5.2 “Power
removed.
In Features, on page 2: Required Power Supply updated, 3.0V to 3.6V for VDDOSC and for VDDPLL
Section 11. “Package Drawing” on page
Section 9.6 “Power Management Controller” on page 25
(1)
,” on page
Section 8. “Memories” on page
Section 8.1.2 “Boot Strategies” on page 20
Table 10-1, “Peripheral Identifiers,” on page
Figure 8-1, “AT91SAM9261 Memory Mapping,” on page
10,
Supplies”, startup voltage slope requirements for VDDCORE and VDDBU added.
Consumption”, startup voltage slope requirements for VDDCORE and VDDBU
Strategies”, removed sentence pertaining to “remap”
10.
to show full product memory mapping.
and
Section 5.2 “Power Consumption” on page
Figure 8-1, “AT91SAM9261 Memory Mapping,” on page
25.
Section 3-1 “Signal Description by Peripheral” on page 5
11.
Section 6.5 “Shutdown Logic Pins” on page
Table 4-1, “AT91SAM9261 Pinout for 217-ball LFBGA
16. Inserted new
ROM”, added NANDFlash Boot.
39.
Table 8-3, “Internal Memory Mapping,” on page
32, Note added to “PB3” comments
33,
to replace Boot ROM section.
28.
Section 10.11 “Timer Counter” on page
Figure 8-1, “AT91SAM9261 Memory
Table 3-1, “Signal Description by
and
25, in the master memory
Figure 9-3, “Power Management
11.
16.
6062LS–ATARM–23-Mar-09
12.
16.
and in
18.