AT91SAM9261B-CU Atmel, AT91SAM9261B-CU Datasheet - Page 17

• Manufacturer Part Number: AT91SAM9261B-CU
• Description: MCU ARM9 ULTRA LOW PWR 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 240MHz
• Total Internal Ram Size: 160KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/3.3V
• Operating Supply Voltage (max): 1.32/1.95/3.6V
• Operating Supply Voltage (min): 1.08/1.65/2.7/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 217
• Package Type: LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 160 KB
• Interface Type: JTAG,SPI, SSC, TWI, UART
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 96
• Ram Memory Size: 160KB
• Cpu Speed: 190MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

8.1
6062LS–ATARM–23-Mar-09
Embedded Memories
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to
8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
The area 0 is reserved for the addressing of the internal memories, and a second level of decod-
ing provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and
provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
The Bus Matrix manages five Masters and five Slaves.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master.
Regarding Master 0 and Master 1 (ARM926
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to
Table 8-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave.
Table 8-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• 32 KB ROM
• 160 KB Fast SRAM
– Single Cycle Access at full bus speed
– Single Cycle Access at full bus speed
– Supports ARM926EJ-S TCM interface at full processor speed
List of Bus Matrix Masters
List of Bus Matrix Slaves
Table 8-3
for details.
AT91SAM9261 Preliminary
™
Instruction and Data), three different Slaves are
ARM926 Data
PDC
LCD Controller
USB Host
ARM926 Instruction
Internal SRAM
Internal ROM
LCD Controller and USB Host Port Interfaces
External Bus Interface
Internal Peripherals
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