PIC17C752-16/L Microchip Technology, PIC17C752-16/L Datasheet - Page 57

• Manufacturer Part Number: PIC17C752-16/L
• Description: IC MCU OTP 8KX16 A/D PWM 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C752-16/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 50
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Controller Family/series: PIC17
• No. Of I/o's: 50
• Ram Memory Size: 678Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.8
The BSR is used to switch between banks in the data
memory area (Figure 7-9). In the PIC17C7XX devices,
the entire byte is implemented. The lower nibble is
used to select the peripheral register bank. The upper
nibble is used to select the general purpose memory
bank.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked. The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank to
FIGURE 7-9:
Note 1: For the SFRs only Banks 0 through 8 are implemented. Selection of an unimplemented bank is not recommended.
Address
Range
2000 Microchip Technology Inc.
10h
17h
20h
FFh
2: For the GPRs, Bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimplemented bank
3: SFR Bank 8 is only implemented on the PIC17C76X.
BSR
7
Bank Select Register (BSR)
(2)
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
is not recommended.
4 3
Bank 0
Bank 0
(1)
0
0
0
BSR OPERATION
Bank 1
Bank 1
1
1
Bank 2
Bank 2
2
2
Bank 3
Bank 3
3
3
Bank 4
Bank 4
4
4
Bank 5
5
Bank 6
bank in order to address all peripherals related to a sin-
gle task. To assist this, a MOVLB bank instruction has
been included in the instruction set.
The need for a large general purpose memory space
dictated a general purpose RAM banking scheme. The
upper nibble of the BSR selects the currently active
general purpose RAM bank. To assist this, a MOVLR
bank instruction has been provided in the instruction
set.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is
completed to the bit bucket and the ALU status bits will
be set/cleared as appropriate.
6
Note:
Bank 7
7
Registers in Bank 15 in the Special Func-
tion Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
Bank 8
8
Bank 15
Bank 15
PIC17C7XX
15
15
SFR
Banks
GPR
Banks
DS30289B-page 57
(Peripheral)
(RAM)