PIC18F6585-I/PT Microchip Technology, PIC18F6585-I/PT Datasheet - Page 15

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6585-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.2.1
The programming example presented in Section 3.2
“Code Memory Programming” utilizes multi-panel
programming. This technique greatly decreases the
total amount of time necessary to completely program
a device and is the recommended method of
completely programming a device.
There may be situations, however, where it is advanta-
geous to limit writes to a single panel. In such cases,
the user only needs to disable the multi-panel write
feature of the device by appropriately configuring the
Programming Control register located at 3C0006h.
The single panel that will be written will automatically
be enabled based on the value of the Table Pointer.
3.2.2
All of the programming examples up to this point have
assumed that the device has been Bulk Erased prior to
programming (see Section 3.1 “High-Voltage ICSP
Bulk Erase”). However, it may be the case that the
user wishes to modify only a section of an already
programmed device.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by placing the
device in Single Panel Write mode (see Section 3.2.1
“Single Panel Programming”), loading the 8-byte
write buffer for the panel and then initiating a write
sequence. In this case, it is assumed that the address
space to be written already has data in it (i.e., it is not
blank).
 2010 Microchip Technology Inc.
Note:
SINGLE PANEL PROGRAMMING
Even though multi-panel writes are dis-
abled, the user must still fill the 8-byte
write buffer for the given panel.
MODIFYING CODE MEMORY
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte target space prior to writing the data.
When using the EECON1 register to act on code mem-
ory, the EEPGD bit must be set (EECON1<7> = 1) and
the CFGS bit must be cleared (EECON1<6> = 0). The
WREN bit must be set (EECON1<2> = 1) to enable
writes of any sort (e.g., erases) and this must be done
prior to initiating a write sequence. The FREE bit must
be set (EECON1<4> = 1) in order to erase the program
space being pointed to by the Table Pointer. The erase
sequence
(EECON1<1> = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The erase will begin on the falling edge of the 4th PGC
after the WR bit is set. After the erase sequence termi-
nates, PGC must still be held low for the time specified
by parameter P10 to allow high-voltage discharge of
the memory array.
PIC18FXX80/XX85
is initiated
by
setting
DS39606E-page 15
the
WR
bit