PIC18F6585-I/PT Microchip Technology, PIC18F6585-I/PT Datasheet
PIC18F6585-I/PT
Specifications of PIC18F6585-I/PT
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PIC18F6585-I/PT Summary of contents
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... Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW This document includes the specifications for the following devices: • PIC18F6585 • PIC18F6680 • PIC18F8585 • PIC18F8680 2.0 PROGRAMMING OVERVIEW PIC18FXX80/XX85 devices can be programmed using either the high-voltage In-Circuit Serial Programming (ICSP TM ) method, or the low-voltage ICSP method. ...
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... RG2/CANRX 5 RG3 6 RG5/MCLR RG4/P1D RF7/SS 11 RF6/AN11/C1IN- 12 RF5/AN10/C1IN+/CV REF 13 RF4/AN9/C2IN- 14 RF3/AN8/C2IN+ 15 RF2/AN7/C1OUT 16 Note 1: CCP2 pin placement depends on the Processor mode settings. DS39606E-page PIC18F6X8X RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1/PGM 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1/P1A 2010 Microchip Technology Inc. ...
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... RG1/CANTX2 14 RG2/CANRX 15 RG3 16 RG5/MCLR RG4/P1D N RF7/SS RF6/AN11/C1IN- 22 RF5/AN10/C1IN+/CV 23 REF RF4/AN9/C2IN- 24 RF3/AN8/C2IN RF2/AN7/C1OUT Note 1: CCP2 pin placement depends on the Processor mode settings. 2010 Microchip Technology Inc. PIC18FXX80/XX85 Top View PIC18F6X8X RB0/INT0 59 RB1/INT1 58 RB2/INT2 57 RB3/INT3 56 RB4/KBI0 55 RB5/KBI1/PGM 54 RB6/KBI2/PGC N/C 51 OSC2/CLKO/RA6 50 OSC1/CLKI ...
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... RH6/AN14/P1C Note 1: PSP is available only in Microcontroller mode. 2: CCP2 pin placement depends on the Processor mode settings. DS39606E-page PIC18F8X8X RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 56 (2) RB3/INT3/CCP2 55 RB4/KBI0 54 RB5/KBI1/PGM 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 OSC1/CLKI RB7/KBI3/PGD 47 RC5/SDO 46 RC4/SDI/SDA 45 RC3/SCK/SCL 44 RC2/CCP1/P1A 43 RJ7/UB 42 RJ6/ 2010 Microchip Technology Inc. ...
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... Note: Sizes of memory areas are not shown to scale. 2010 Microchip Technology Inc. PIC18FXX80/XX85 TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Code Memory Size Device (Bytes) PIC18F6585 0000h - 00BFFFh (48K) PIC18F8585 PIC18F6680 0000h -00FFFFh (64K) PIC18F8680 48 Kbytes 64 Kbytes Boot Block Boot Block Panel 1 ...
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... ID Location 8 CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H CONFIG4L CONFIG4H CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H Device ID1 Device ID2 2010 Microchip Technology Inc. TBLPTRL Addr[7:0] 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h 300000h 300001h 300002h 300003h 300004h 300005h 300006h ...
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... FIGURE 2-6: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P12 P1 D110 MCLR PGD PGC PGD = Input 2010 Microchip Technology Inc. PIC18FXX80/XX85 FIGURE 2-7: HIGH-LEVEL PROGRAMMING FLOW Start Perform Bulk Erase Program Memory Program IDs Program Data Verify Program Verify IDs Verify Data ...
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... C 16-Bit Data Payload PGD = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Table Write, post-increment P5A Fetch Next 4-Bit Command 2010 Microchip Technology Inc. ...
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... FIGURE 3-2: BULK ERASE TIMING PGC P5 P5A PGD 4-Bit Command 16-Bit Data Payload 2010 Microchip Technology Inc. PIC18FXX80/XX85 TABLE 3-2: 4-Bit Command Payload 0000 8E A6 0000 8C A6 0000 0E 3C 0000 6E F8 0000 0E 00 0000 6E F7 0000 0E 04 0000 6E F6 1100 00 80 ...
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... MOVLW 06h MOVWF TBLPTRL Write 40h to 3C0006h to enable multi-panel erase. BSF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, FREE CLRF TBLPTRU CLRF TBLPTRH CLRF TBLPTRL Write 2 dummy bytes and start programming. NOP - hold PGC high for time P9. 2010 Microchip Technology Inc. ...
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... In this case, the offset of the write within each panel is the same (see Figure 3-4). Multi-Panel Write mode is enabled by appropriately configuring the Programming Control register located at 3C0006h. 2010 Microchip Technology Inc. PIC18FXX80/XX85 Start Addr = 0 Configure Device for ...
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... Panel 1 TBLPTR<21:13> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> Offset = TBLPTR<12:3> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS39606E-page 12 Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> 2010 Microchip Technology Inc. ...
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... To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented each panel at each iteration of the loop. 2010 Microchip Technology Inc. PIC18FXX80/XX85 Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS BSF EECON1, WREN ...
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... All No Panel Buffers Written? Yes Start Write Sequence and Hold PGC High until Done Delay P9 + P10 Time for Write to Occur All No Locations Done? Yes Done P5A 4-Bit Command PGD = Input P10 16-Bit Programming Time Data Payload 2010 Microchip Technology Inc. ...
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... In this case assumed that the address space to be written already has data in it (i.e not blank). 2010 Microchip Technology Inc. PIC18FXX80/XX85 The minimum amount of code memory that may be erased at a given time is 64 bytes. Again, the device must be placed in Single Panel Write mode ...
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... MOVLW <Addr[8:15]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold PGC high for time P9 2010 Microchip Technology Inc. ...
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... PGC P5 PGD 4-Bit Command BSF EECON1 PGC Poll WR Bit PGD 4-Bit Command 2010 Microchip Technology Inc. PIC18FXX80/XX85 FIGURE 3-7: P5A Poll WR Bit, Repeat Until Clear (see below) PGD = Input P5A 4-Bit Command MOVF EECON1 MOVWF TABLAT PGD = Input PROGRAM DATA FLOW ...
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... EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH MOVLW <Data> MOVWF EEDATA BSF EECON1, WREN MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR MOVF EECON1 MOVWF TABLAT (1) Shift out data BCF EECON1, WREN 2010 Microchip Technology Inc. ...
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... In order to modify the ID locations, refer to the method- ology described in Section 3.2.2 “Modifying Code Memory”. As with code memory, the ID locations must be erased before modified. 2010 Microchip Technology Inc. PIC18FXX80/XX85 Note: Even though multi-panel writes are dis- abled, the user must still fill the 8-byte data buffer for the panel ...
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... MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 to program two consecutive four between every NOPs 2010 Microchip Technology Inc. ...
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... FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW Start Load Even Configuration Address Program LSB Delay P9 Time for Write Execute Four NOPs Done 2010 Microchip Technology Inc. PIC18FXX80/XX85 Start Load Odd Configuration Address Program MSB Delay P9 Time for Write Execute Four NOPs Done ...
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... ID and Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output P5A MSb Fetch Next 4-Bit Command PGD = Input 2010 Microchip Technology Inc. ...
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... All No Code Memory Verified? Yes 2010 Microchip Technology Inc. PIC18FXX80/XX85 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code mem- ory has been verified. The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer beyond the code memory space ...
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... EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT (1) Shift Out Data READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No Done ? Yes Done 2010 Microchip Technology Inc. ...
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... Checking” a device merely means to verify that all bytes read as FFh, except the Configuration bits. Unused (reserved) Configuration bits will read ‘0’ (pro- grammed). Refer to Table 5-2 for blank configuration expect data for the various PIC18FXX80/XX85 devices. 2010 Microchip Technology Inc. PIC18FXX80/XX85 ...
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... The Device ID Word for the PIC18FXX80/XX85 devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally even after code or read-protected. TABLE 5-1: DEVICE ID VALUES Device PIC18F6585 PIC18F6680 PIC18F8585 PIC18F8680 DS39606E-page 26 5.3 Low-Voltage Programming (LVP) Bit The LVP bit in Configuration register, CONFIG4L, enables low-voltage ICSP programming ...
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... Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F6X8X devices; maintain this bit set. 2: Unimplemented in PIC18FX585 devices; maintain this bit set. 3: Reserved in PIC18F6X8X devices; maintain this bit set. 2010 Microchip Technology Inc. PIC18FXX80/XX85 Bit 5 Bit 4 Bit 3 Bit 2 OSCSEN — ...
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... Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) 2010 Microchip Technology Inc. ...
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... Unimplemented in PIC18F6X8X (64-pin) devices; maintain this bit set. 2: Unimplemented in PIC18FX585 devices; maintain this bit set. 3: Reserved for PIC18F6X8X devices; maintain this bit set. 2010 Microchip Technology Inc. PIC18FXX80/XX85 Description External Bus Data Wait Enable bit 1 = Wait selections unavailable 0 = Wait selections determined by WAIT1:WAIT0 bits of MEMCOM register ...
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... These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. Device ID bits These bits are used with the DEV10:DEV3 bits in the DEVID2 register to identify part number. These bits are used to indicate the revision of the device. 2010 Microchip Technology Inc. ...
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... An option to not include the Configu- ration Word information may be provided. When embedding Configuration Word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. PIC18FXX80/XX85 5 ...
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... SUM(IDs) PIC18F6585 Boot/ SUM(8000:0BFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) + Block 0/ (CFGW2L & ...
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... Legend: Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2010 Microchip Technology Inc. PIC18FXX80/XX85 Checksum 0AAh at 0 Blank and Max Value Address 036Fh 02C5h 0FB47h 0FAEDh ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39606E-page 34 Checksum 2010 Microchip Technology Inc. 0AAh at 0 Blank and Max Value Address 0C3DAh 0C330h 0BBC0h 0BB57h 43BDh 4354h ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 0AAh at 0 Blank ...
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... V ; this can cause spurious program IL IHH (for LP, HS, HS/PLL and XT modes only) OSC is the Power-up Timer period and T PWRT Conditions Normal programming V Bulk Erase operations meet AC specifications (Note 1) is the oscillator period. OSC 2010 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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