PIC18F6585-I/PT Microchip Technology, PIC18F6585-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6585-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18FXX80/XX85
3.1.1
When using low-voltage ICSP, the part must be sup-
plied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.2 “ICSP Multi-Panel Single Row Erase”
and Section 3.2.2 “Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.3
“Data EEPROM Programming” and write ‘1’s to the
array.
3.1.2
Irrespective of whether high or low-voltage ICSP is
used, it is possible to erase single row (64 bytes of data)
in all panels at once. For example, in the case of a
64-Kbyte device (8 panels), 512 bytes through 64 bytes
in each panel can be erased simultaneously during
each erase sequence. In this case, the offset of the
TABLE 3-3:
DS39606E-page 10
Step 1: Direct access to configuration memory.
Step 2: Configure device for multi-panel writes.
Step 3: Direct access to code memory and enable erase.
Step 4: Erase single row of all panels at an offset.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1111
0000
4-Bit
LOW-VOLTAGE ICSP BULK ERASE
ICSP MULTI-PANEL SINGLE ROW
ERASE
8E A6
8C A6
86 A6
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
8E A6
9C A6
88 A6
6A F8
6A F7
6A F6
<DummyLSB>
<DummyMSB>
00 00
ERASE CODE MEMORY CODE SEQUENCE
Data Payload
BSF
BSF
BSF
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel erase.
BSF
BCF
BSF
CLRF
CLRF
CLRF
Write 2 dummy bytes and start programming.
NOP - hold PGC high for time P9.
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, EEPGD
EECON1, CFGS
EECON1, FREE
TBLPTRU
TBLPTRH
TBLPTRL
erase within each panel is the same (see Figure 3-5).
Multi-panel single row erase is enabled by appropriately
configuring the Programming Control register located at
3C0006h.
The multi-panel single row erase duration is externally
timed and is controlled by PGC. After a “Start Program-
ming” command is issued (4-bit, ‘1111’), a NOP is
issued, where the 4th PGC is held high for the duration
of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time spec-
ified by parameter P10 to allow high-voltage discharge
of the memory array.
The code sequence to program a PIC18FXX80/XX85
device is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18FXX80/XX85 device. The timing dia-
gram that details the “Start Programming” command
and parameters P9 and P10 is shown in Figure 3-6.
Note:
Core Instruction
The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
 2010 Microchip Technology Inc.