PIC18LF442-I/ML Microchip Technology, PIC18LF442-I/ML Datasheet - Page 234
![IC MCU FLASH 8KX16 EE A/D 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF442-I/ML
Manufacturer Part Number
PIC18LF442-I/ML
Description
IC MCU FLASH 8KX16 EE A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16LF627A-IP.pdf
(8 pages)
3.PIC18F242-ISO.pdf
(332 pages)
4.PIC18F242-ISO.pdf
(14 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(16 pages)
7.PIC18F242-ISO.pdf
(14 pages)
8.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18LF442-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC16LF627A-IP PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18F242-ISO PDF datasheet #7
- PIC18LF242-ISO PDF datasheet #8
- Current page: 234 of 332
- Download datasheet (6Mb)
PIC18FXX2
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
DS39564C-page 232
Q Cycle Activity:
After Instruction
operation
Decode
PC =
No
Q1
Read literal
Address (THERE)
operation
Unconditional Branch
[ label ]
0
k
None
GOTO allows an unconditional
branch anywhere within entire
2 Mbyte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTO is always a two-cycle
instruction.
2
2
'k'<7:0>,
GOTO THERE
1110
1111
No
Q2
k
PC<20:1>
1048575
GOTO k
k
1111
19
operation
operation
kkk
No
No
Q3
k
kkkk
7
kkk
Read literal
Write to PC
’k’<19:8>,
operation
No
Q4
kkkk
kkkk
0
8
INCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
C
DC
CNT
Z
C
DC
Q1
=
=
=
=
=
=
=
=
register 'f'
Increment f
[ label ]
0
d
a
(f) + 1
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in W. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
INCF
C, DC, N, OV, Z
Read
0010
Q2
0xFF
0
?
?
0x00
1
1
1
f
[0,1]
[0,1]
© 2006 Microchip Technology Inc.
255
dest
INCF
10da
CNT, 1, 0
Process
Data
Q3
f [,d [,a]
ffff
destination
Write to
Q4
ffff
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