ATMEGA645V-8AU Atmel, ATMEGA645V-8AU Datasheet - Page 56
ATMEGA645V-8AU
Manufacturer Part Number
ATMEGA645V-8AU
Description
IC AVR MCU FLASH 64K 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16MU.pdf
(362 pages)
Specifications of ATMEGA645V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, UART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
54
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
8MHz
No. Of Timers
3
Rohs Compliant
Yes
Data Rom Size
2 KB
Height
1 mm
Length
14 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
14 mm
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.2
12.2.1
2570M–AVR–04/11
Register Description
EICRA – External Interrupt Control Register A
Figure 12-1. Pin Change Interrupt
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-1.
Bit
(0x69)
Read/Write
Initial Value
ISC01
0
0
1
1
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
ISC00
pin_lat
Interrupt 0 Sense Control
PCINT(0)
PCIF
R
7
–
0
0
1
0
1
clk
clk
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
LE
R
6
–
0
Table
pin_lat
D
12-1. The value on the INT0 pin is sampled before detecting
R
5
–
0
Q
pin_sync
PCINT(0) in PCMSK(x)
4
–
R
0
ATmega325/3250/645/6450
pcint_in_(0)
R
3
–
0
0
x
clk
R
2
–
0
pcint_syn
ISC01
R/W
1
0
pcint_setflag
ISC00
R/W
0
0
EICRA
PCIF
56
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