PIC18LF248-I/SO Microchip Technology, PIC18LF248-I/SO Datasheet - Page 203
![IC MCU CAN FLASH 8K 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF248-I/SO
Manufacturer Part Number
PIC18LF248-I/SO
Description
IC MCU CAN FLASH 8K 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 203 of 402
- Download datasheet (7Mb)
19.2
There are many control and data registers associated
with the CAN module. For convenience, their
descriptions have been grouped into the following
sections:
• Control and Status Registers
• Transmit Buffer Registers (Data and Control)
• Receive Buffer Registers (Data and Control)
• Baud Rate Control Registers
• I/O Control Register
• Interrupt Status and Control Registers
REGISTER 19-1:
© 2006 Microchip Technology Inc.
Note:
CAN Module Registers
bit 7-5
bit 4
bit 3-1
bit 0
Not all CAN registers are available in the
Access Bank.
CANCON: CAN CONTROL REGISTER
bit 7
REQOP2:REQOP0: Request CAN Operation Mode bits
1xx = Request Configuration mode
011 = Request Listen Only mode
010 = Request Loopback mode
001 = Request Disable mode
000 = Request Normal mode
ABAT: Abort All Pending Transmissions bit
1 = Abort all pending transmissions (in all transmit buffers)
0 = Transmissions proceeding as normal
WIN2:WIN0: Window Address bits
This selects which of the CAN buffers to switch into the Access Bank area. This allows access
to the buffer registers from any data memory bank. After a frame has caused an interrupt, the
ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See
Example 19-1 for code example.
111 = Receive Buffer 0
110 = Receive Buffer 0
101 = Receive Buffer 1
100 = Transmit Buffer 0
011 = Transmit Buffer 1
010 = Transmit Buffer 2
001 = Receive Buffer 0
000 = Receive Buffer 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
REQOP2
R/W-1
REQOP1
R/W-0
REQOP0
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
ABAT
19.2.1
The registers described in this section control the
overall operation of the CAN module and show its
operational status.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
WIN2
CAN CONTROL AND STATUS
REGISTERS
R/W-0
WIN1
PIC18FXX8
x = Bit is unknown
R/W-0
WIN0
DS41159E-page 201
U-0
—
bit 0
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