PIC18LF248-I/SO Microchip Technology, PIC18LF248-I/SO Datasheet - Page 147
![IC MCU CAN FLASH 8K 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF248-I/SO
Manufacturer Part Number
PIC18LF248-I/SO
Description
IC MCU CAN FLASH 8K 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 147 of 402
- Download datasheet (7Mb)
REGISTER 17-2:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0000 = SPI Master mode, clock = F
Legend:
R = Readable bit
-n = Value at POR
WCOL
R/W-0
Note:
Note:
Note:
(must be cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user
must read the SSPBUF even if only transmitting data to avoid setting overflow (must be
cleared in software).
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in
I
2
SSPOV
C mode only.
R/W-0
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
OSC
OSC
OSC
R/W-0
CKP
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
PIC18FXX8
x = Bit is unknown
SSPM1
R/W-0
DS41159E-page 145
SSPM0
R/W-0
bit 0
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