PIC18LF4525-I/ML Microchip Technology, PIC18LF4525-I/ML Datasheet
PIC18LF4525-I/ML
Specifications of PIC18LF4525-I/ML
Related parts for PIC18LF4525-I/ML
PIC18LF4525-I/ML Summary of contents
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... PIC18F2525/2620/4525/4620 Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2008 Microchip Technology Inc. Data Sheet 28/40/44-Pin DS39626E ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4525 48K 24576 PIC18F4620 64K 32768 © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 ...
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... RA0/AN0 2 39 RA1/AN1 3 38 -/CV REF REF ( RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 © 2008 Microchip Technology Inc. ...
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... QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: For the QFN package recommended that the bottom pad be connected to V © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 RC0/T1OSO/T13CKI 32 2 OSC2/CLKO/RA6 31 3 OSC1/CLKI/RA7 30 4 PIC18F4525 ...
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... Appendix E: Migration from Mid-Range TO Enhanced Devices ........................................................................................................ 396 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 396 Index .................................................................................................................................................................................................. 397 The Microchip Web Site ..................................................................................................................................................................... 407 Customer Change Notification Service .............................................................................................................................................. 407 Customer Support .............................................................................................................................................................................. 407 Reader Response .............................................................................................................................................................................. 408 PIC18F2525/2620/4525/4620 Product Identification System ............................................................................................................ 409 DS39626E-page 4 © 2008 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS39626E-page 5 ...
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... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 6 © 2008 Microchip Technology Inc. ...
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... PIC18F2525 • PIC18LF2525 • PIC18F2620 • PIC18LF2620 • PIC18F4525 • PIC18LF4525 • PIC18F4620 • PIC18LF4620 This family offers the advantages of all PIC18 microcontrollers – namely, high computational perfor- mance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. ...
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... Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2620), accommodate an operating V range of 4.2V to 5.5V. DD Low-voltage parts, designated by “LF” (such as PIC18LF2620), function over an extended V of 2.0V to 5.5V. © 2008 Microchip Technology Inc. for for range DD ...
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... Input Channels 10 Input Channels 13 Input Channels Resets (and Delays) RESET Instruction, Stack Underflow MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Packages © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 PIC18F2525 PIC18F2620 DC – 40 MHz DC – 40 MHz 49152 65536 24576 32768 3968 3968 ...
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... PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT (3) OSC2/CLKO /RA6 (3) OSC1/CLKI /RA7 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (2) MCLR/V /RE3 PP © 2008 Microchip Technology Inc. ...
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... RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Data Bus<8> Data Latch ...
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... Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2008 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description . SS © 2008 Microchip Technology Inc. ...
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... Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 3: For the QFN package recommended that the bottom pad be connected to V © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description . SS © 2008 Microchip Technology Inc. ...
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... Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 3: For the QFN package recommended that the bottom pad be connected to V © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... Enhanced CCP1 output. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input P = Power Description . SS © 2008 Microchip Technology Inc. ...
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... Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 3: For the QFN package recommended that the bottom pad be connected to V © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 22 © 2008 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... FIGURE 2-4: Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2008 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Section 2.6.5.1 “Compensating with the EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used. or temperature changes, which can compensation techniques are © 2008 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 R/W-0 R/W-0 ...
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... OSCTUNE<7> LP, XT, HS, RC, EC Peripherals T1OSC Internal Oscillator CPU IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2008 Microchip Technology Inc. ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. DS39626E-page 30 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others) ...
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... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 32 © 2008 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. © 2008 Microchip Technology Inc. ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) T (1) OST T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set ; (approx). These intervals are not shown to scale. PLL . OSC © 2008 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the is CSD Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2008 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... None LP, XT OST HSPLL T OST EC CSD (2) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (3) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS © 2008 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after Power-on Reset). DS39626E-page 42 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 FIGURE 4- ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. © 2008 Microchip Technology Inc. ...
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... Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39626E-page 46 T PWRT T OST T PWRT T OST T PWRT T OST © 2008 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 , V RISE > PWRT T OST T PWRT T OST ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( STKPTR Register POR BOR STKFUL STKUNF © 2008 Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Reset Vector High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector On-Chip Program Memory Read ‘0’ © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 RCALL or interrupt, the can return these values to Stack Pointer STKPTR<4:0> 00010 © 2008 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 “Table Reads and Table Writes”. © 2008 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2008 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2008 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Data Memory 000h ...
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... F90h — (2) F8Fh — (2) F8Eh — (3) F8Dh LATE (3) F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA (2) F88h — (1) (2) F87h — (2) F86h — (2) F85h — (3) F84h PORTE (3) F83h PORTD F82h PORTC F81h PORTB F80h PORTA © 2008 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 4 Bit 3 ...
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... PDC1 PDC0 51, 156 0000 0000 (2) (2) PSSBD1 PSSBD0 51, 157 0000 0000 CVR1 CVR0 51, 239 0000 0000 CM1 CM0 51, 233 0000 0111 51, 137 xxxx xxxx 51, 137 xxxx xxxx TMR3CS TMR3ON 51, 135 0000 0000 © 2008 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 4 Bit 3 ...
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... Table 24-2 and Table 24-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The Access RAM bit, ‘a’, determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2008 Microchip Technology Inc. ...
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... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... F00h Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory © 2008 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... Bank 0 addresses below 5Fh can still be addressed F80h by using the BSR. FFFh © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘ ...
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... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 72 © 2008 Microchip Technology Inc. ...
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... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The EECON1 register (Register 6-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
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... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39626E-page 74 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
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... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts information (e.g., program © 2008 Microchip Technology Inc. ...
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... EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — — — ...
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... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 78 © 2008 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT © 2008 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 R/W-x R/W-0 ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> TBLPTRL 0 TABLE WRITE TBLPTR<5:0> © 2008 Microchip Technology Inc. ...
Page 85
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 86
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2008 Microchip Technology Inc. ...
Page 87
... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...
Page 88
... BUFFER_ADDR_LOW FSR0L D’64 ; number of bytes in holding register COUNTER POSTINC0, WREG ; get low byte of buffer data TABLAT ; present data to table latch ; write data, perform a short write ; to internal TBLWT holding register. COUNTER ; loop until buffers are full WRITE_WORD_TO_HREGS © 2008 Microchip Technology Inc. ...
Page 89
... PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ...
Page 90
... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 88 © 2008 Microchip Technology Inc. ...
Page 91
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
Page 92
... WREG ; ADDWFC RES3 BTFSS ARG2H ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L SUBWF RES2 ; MOVF ARG1H SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L SUBWF RES2 ; MOVF ARG2H SUBWFB RES3 ; CONT_CODE : © 2008 Microchip Technology Inc ...
Page 93
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...
Page 94
... System cycle clock output (F modes. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. I ANA Main oscillator input connection. I ANA Main clock input connection. Description /4) in RC, INTIO1 and EC Oscillator OSC © 2008 Microchip Technology Inc. ...
Page 95
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 5 Bit 4 ...
Page 96
... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the Configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). © 2008 Microchip Technology Inc. will end the ...
Page 97
... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD is enabled. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 I/O I/O Type ...
Page 98
... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 49 — RBIP 49 INT2IF INT1IF 49 PCFG1 PCFG0 51 © 2008 Microchip Technology Inc. ...
Page 99
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Note Power-on Reset, these pins are configured as digital inputs ...
Page 100
... LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (EUSART module). O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Description © 2008 Microchip Technology Inc. ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset ...
Page 102
... EXAMPLE 9-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2008 Microchip Technology Inc. ...
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... P1D 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 I/O I/O Type O DIG LATD<0> data output. ...
Page 104
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39626E-page 102 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 52 CCP1M1 CCP1M0 51 © 2008 Microchip Technology Inc. ...
Page 105
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 106
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39626E-page 104 R/W-0 U-0 R/W-1 — PSPMODE TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 107
... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 I/O I/O ...
Page 108
... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2008 Microchip Technology Inc. ...
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... PSPIE ADIE (1) IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 5 ...
Page 110
... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 108 © 2008 Microchip Technology Inc. ...
Page 111
... Individual interrupts can be disabled through their corresponding enable bits. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 112
... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2008 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 113
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T condition and allow the bit to be cleared. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Note: Interrupt flag bits are set when an interrupt ...
Page 114
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39626E-page 112 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 115
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 ...
Page 116
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 117
... A TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 118
... Disables the TMR1 overflow interrupt Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. DS39626E-page 116 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 119
... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
Page 120
... Low priority Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. DS39626E-page 118 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 121
... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 122
... The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 4.1 “RCON Register”. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 123
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 10.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 122 © 2008 Microchip Technology Inc. ...
Page 125
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 126
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 127
... RA6 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 128
... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 126 © 2008 Microchip Technology Inc. ...
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... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 130
... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 131
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 132
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2008 Microchip Technology Inc. ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 134
... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 132 © 2008 Microchip Technology Inc. ...
Page 135
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 136
... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP © 2008 Microchip Technology Inc. ...
Page 137
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 138
... Clear TMR3 TMR3L 8 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 139
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 140
... PIC18F2525/2620/4525/4620 NOTES: DS39626E-page 138 © 2008 Microchip Technology Inc. ...
Page 141
... I/O state) 1011 = Compare mode, trigger special event; reset timer; CCPx match starts A/D conversion (CCPxIF bit is set) 11xx = PWM mode © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules ...
Page 142
... Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropri- ate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction © 2008 Microchip Technology Inc. ...
Page 143
... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 144
... Set CCP1IF Output Compare Logic Match 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2008 Microchip Technology Inc. ...
Page 145
... The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Bit 5 Bit 4 ...
Page 146
... CCPR2H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2008 Microchip Technology Inc. ...
Page 147
... The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 EQUATION 15-3: PWM Resolution (max) Note: ...
Page 148
... CCP2M2 PSSAC1 PSSAC0 PSSBD1 (2) (2) (2) PDC5 PDC4 PDC3 PDC2 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 51 (2) (2) PSSBD0 51 (2) (2) (2) PDC1 PDC0 51 © 2008 Microchip Technology Inc. ...
Page 149
... PWM mode, P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode, P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode, P1A, P1C active-low; P1B, P1D active-low © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, ...
Page 150
... PWM. and Timer RC2 RD5 All 40/44-pin devices: CCP1 RD5/PSP5 P1A P1B P1A P1B and Section 15.3 “Compare the processes described in “Setup for PWM RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2008 Microchip Technology Inc. ...
Page 151
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 152
... The general relationship of the outputs in all configurations is summarized in Figure 16-2. 9.77 kHz 39.06 kHz FFh FFh OSC ) log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2008 Microchip Technology Inc. ...
Page 153
... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (see Section 16.4.6 “Programmable Dead-Band Delay”). © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 0 Duty Cycle Period (1) Delay Delay 0 Duty ...
Page 154
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2008 Microchip Technology Inc. ...
Page 155
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 156
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2008 Microchip Technology Inc. ...
Page 157
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...
Page 158
... R/W-0 R/W-0 (1) (1) (1) PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( cycles, between the scheduled and actual time for a PWM OSC OSC R/W-0 R/W-0 R/W-0 (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 159
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Unimplemented on 28-pin devices; bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
Page 160
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle ECCPASE Cleared by Firmware © 2008 Microchip Technology Inc. ...
Page 161
... Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 162
... Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP 52 TMR3IF CCP2IF 52 TMR3IE CCP2IE 52 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 51 (2) (2) PSSBD1 PSSBD0 51 (2) (2) (2) PDC2 PDC1 PDC0 51 © 2008 Microchip Technology Inc. ...
Page 163
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four SPI modes are supported ...
Page 164
... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 165
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 R/W-0 R/W-0 (2) (3) ...
Page 166
... Note: The SSPBUF register cannot be used with read-modify-write instructions such as BCF, BTFSC and COMF, etc. Note: To avoid lost data in Master mode, a read of the SSPBUF must be performed to clear the Buffer Full (BF) detect bit (SSPSTAT<0>) between each transmission. © 2008 Microchip Technology Inc. ...
Page 167
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers ...
Page 168
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2008 Microchip Technology Inc. ...
Page 169
... SSPIF Interrupt Flag SSPSR to SSPBUF © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
Page 170
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39626E-page 168 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 3 bit 2 bit 5 bit bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2008 Microchip Technology Inc. ...
Page 171
... These bits are unimplemented on 28-pin devices and read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
Page 172
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When the © 2008 Microchip Technology Inc. ...
Page 173
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 2 C™ MODE) ...
Page 174
... DS39626E-page 172 2 C™ MODE) R/W-0 R/W-0 (1) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /(4 * (SSPADD + 1)) OSC R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown 2 C conditions were not valid for a (2) © 2008 Microchip Technology Inc. ...
Page 175
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 2 C™ MODE) ...
Page 176
... Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits, SSPIF and BF, are set). 9. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. © 2008 Microchip Technology Inc. ...
Page 177
... The clock must be released by setting bit, CKP (SSPCON<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 178
... PIC18F2525/2620/4525/4620 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39626E-page 176 © 2008 Microchip Technology Inc. ...
Page 179
... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS39626E-page 177 ...
Page 180
... PIC18F2525/2620/4525/4620 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39626E-page 178 © 2008 Microchip Technology Inc. ...
Page 181
... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS39626E-page 179 ...
Page 182
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 17-11). © 2008 Microchip Technology Inc. ...
Page 183
... SDA DX SCL CKP WR SSPCONx © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...
Page 184
... PIC18F2525/2620/4525/4620 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39626E-page 182 © 2008 Microchip Technology Inc. ...
Page 185
... FIGURE 17-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS39626E-page 183 ...
Page 186
... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ © 2008 Microchip Technology Inc. ...
Page 187
... Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 188
... SSPCON2 register. 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2008 Microchip Technology Inc. ...
Page 189
... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 190
... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2008 Microchip Technology Inc. ...
Page 191
... FIGURE 17-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
Page 192
... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG 1st bit Write to SSPBUF occurs here T BRG Sr = Repeated Start T BRG © 2008 Microchip Technology Inc. ...
Page 193
... WCOL bit is set and SSPBUF is CY updated. This may result in a corrupted transfer. The user should verify that the WCOL flag is clear after each write to SSPBUF to ensure the transfer is correct. © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
Page 194
... PIC18F2525/2620/4525/4620 2 FIGURE 17-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39626E-page 192 © 2008 Microchip Technology Inc. ...
Page 195
... FIGURE 17-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS39626E-page 193 ...
Page 196
... PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition later, the PEN bit is BRG Cleared in software BRG © 2008 Microchip Technology Inc. ...
Page 197
... FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
Page 198
... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software © 2008 Microchip Technology Inc. ...
Page 199
... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2008 Microchip Technology Inc. PIC18F2525/2620/4525/4620 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
Page 200
... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG Interrupt cleared in software © 2008 Microchip Technology Inc. ‘0’ ‘0’ ‘0’ ...