PIC18F4431-I/PT Microchip Technology, PIC18F4431-I/PT Datasheet - Page 41

• Manufacturer Part Number: PIC18F4431-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer, and the primary clock is shut
down. When using the INTRC source, this mode pro-
vides the best power conservation of all the run modes,
while still executing code. This mode works well for
user applications that are not highly timing sensitive, or
do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 oscillators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to, and exit
from, RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
This mode is entered by clearing the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
The IRCF bits may be modified at any time to immedi-
ately change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.
FIGURE 3-10:
 2003 Microchip Technology Inc.
INTRC
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Q4
RC_RUN MODE
Q1
PC
Q2
Q3
TIMING TRANSITION TO RC_RUN MODE
Q4
1
Q1
2
3
Clock Transition
PIC18F2331/2431/4331/4431
4
Preliminary
5
PC + 2
6
7
If the IRCF bits are all clear, the INTOSC output is not
enabled, and the IOFS bit will remain clear; there will
be no indication of the current clock source. The INTRC
source is providing the system clocks.
If the IRCF bits are changed from all clear (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable. Clocks to
the system continue while the INTOSC source
stabilizes in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed, and the
INTOSC source was already stable, the IOFS bit will
remain set.
When a wake event occurs, the system continues to be
clocked from the INTOSC multiplexer while the primary
clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the OSTS bit is set and the primary
clock provides the system clock. The IDLEN and SCS
bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
Note:
8
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
Q2
DD
/F
Q3
OSC
specifications are violated.
Q4
DD
Q1
PC + 4
is less than 3V, it is
DS39616B-page 39
Q2
Q3
DD
.