PIC18F4431-I/PT Microchip Technology, PIC18F4431-I/PT Datasheet - Page 211

• Manufacturer Part Number: PIC18F4431-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the Time Base
Period Register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
A PWM update lockout feature may optionally be
enabled so the user may specify when new duty cycle
buffer values are valid. The PWM update lockout
feature is enabled by setting the control bit UDIS in the
PWMCON1 register. This bit affects all Duty Cycle
Buffer registers and the PWM time base period buffer,
PTPER.
To perform a PWM update lockout:
1.
2.
3.
4.
17.14 PWM Special Event Trigger
The PWM module has a special event trigger capability
that allows A/D conversions to be synchronized to the
PWM time base. The A/D sampling and conversion
time may be programmed to occur at any point within
the PWM period. The special event trigger allows the
user to minimize the delay between the time when A/D
conversion results are acquired and the time when the
duty cycle value is updated.
The PWM 16-bit Special Event Trigger register
SEVTCMP (high and low), and five control bits in
PWMCON1 register are used to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register pair.
SEVTDIR bit in PWMCON1 register specifies the
counting phase when the PWM time base is in an
Up/Down Counting mode.
If the SEVTDIR bit is cleared, the special event trigger
will occur on the upward counting cycle of the PWM
time base. If SEVTDIR is set, the special event trigger
will occur on the downward count cycle of the PWM
time base. The SEVTDIR bit has effect only when PWM
timer is in the Up/Down Counting mode.
 2003 Microchip Technology Inc.
Set the UDIS bit.
Write all Duty Cycle registers and PTPER, if
applicable.
Clear the UDIS bit to re-enable updates.
With this, when UDIS bit is cleared, the buffer
values will be loaded to the actual registers. This
makes a synchronous loading of the registers.
PIC18F2331/2431/4331/4431
Preliminary
17.14.1
The PWM module will always produce special event
trigger pulses. This signal may optionally be used by
the A/D module. Refer to Chapter 20.0 "10-bit
High-Speed
Module" for details.
17.14.2
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS3:SEVOPS0 control
bits in the PWMCON1 register.
The special event output postscaler is cleared on any
write to the SEVTCMP register pair, or on any device
Reset.
SPECIAL EVENT TRIGGER ENABLE
SPECIAL EVENT TRIGGER
POSTSCALER
Analog-to-Digital
DS39616B-page 209
Converter
(A/D)