DSPIC33FJ64GP802-E/SO Microchip Technology, DSPIC33FJ64GP802-E/SO Datasheet - Page 395
![IC DSPIC MCU/DSP 64K 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ64GP802-E/SO
Manufacturer Part Number
DSPIC33FJ64GP802-E/SO
Description
IC DSPIC MCU/DSP 64K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP802-E/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
On-chip Dac
2-chx16-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 395 of 402
- Download datasheet (3Mb)
M
Memory Organization.......................................................... 37
Microchip Internet Web Site .............................................. 401
Modes of Operation
Modulo Addressing ............................................................. 65
MPLAB ASM30 Assembler, Linker, Librarian ................... 320
MPLAB ICD 3 In-Circuit Debugger System ...................... 321
MPLAB Integrated Development Environment Software .. 319
MPLAB PM3 Device Programmer .................................... 322
MPLAB REAL ICE In-Circuit Emulator System................. 321
MPLINK Object Linker/MPLIB Object Librarian ................ 320
N
NVM Module
O
Open-Drain Configuration ................................................. 160
Output Compare ............................................................... 197
P
Packaging ......................................................................... 379
Peripheral Module Disable (PMD) .................................... 154
PICkit 2 Development Programmer/Debugger and
PICkit 3 In-Circuit Debugger/Programmer and
Pinout I/O Descriptions (table) ............................................ 17
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 84
Power-Saving Features .................................................... 153
Program Address Space ..................................................... 37
Program Memory
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Disable ...................................................................... 223
Initialization ............................................................... 223
Listen All Messages .................................................. 223
Listen Only ................................................................ 223
Loopback .................................................................. 223
Normal Operation...................................................... 223
Applicability ................................................................. 66
Operation Example ..................................................... 65
Start and End Address................................................ 65
W Address Register Selection .................................... 65
Register Map............................................................... 62
Details ....................................................................... 380
Marking ..................................................................... 379
PICkit 2 Debug Express............................................ 322
PICkit 3 Debug Express............................................ 321
Register Map............................................................... 62
Register Map......................................................... 60, 61
Register Map............................................................... 61
Clock Frequency and Switching................................ 153
Construction................................................................ 68
Data Access from Program Memory
Data Access from Program Memory
Data Access from, Address Generation...................... 69
Memory Map ............................................................... 37
Table Read Instructions
Visibility Operation ...................................................... 71
Interrupt Vector ........................................................... 38
Organization................................................................ 38
Reset Vector ............................................................... 38
Using Program Space Visibility........................... 71
Using Table Instructions ..................................... 70
TBLRDH ............................................................. 70
TBLRDL .............................................................. 70
Preliminary
R
Reader Response............................................................. 402
Register Map
Registers
CRC............................................................................ 60
Dual Comparator ........................................................ 60
Parallel Master/Slave Port .......................................... 59
Real-Time Clock and Calendar .................................. 60
AD1CHS0 (ADC1 Input Channel 0 Select................ 263
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 262
AD1CON1 (ADC1 Control 1) .................................... 257
AD1CON2 (ADC1 Control 2) .................................... 259
AD1CON3 (ADC1 Control 3) .................................... 260
AD1CON4 (ADC1 Control 4) .................................... 261
AD1CSSL (ADC1 Input Scan Select Low) ............... 264
AD1PCFGL (ADC1 Port Configuration Low) ............ 264
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 233
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 234
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 234
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 235
CiCFG1 (ECAN Baud Rate Configuration 1)............ 231
CiCFG2 (ECAN Baud Rate Configuration 2)............ 232
CiCTRL1 (ECAN Control 1) ...................................... 224
CiCTRL2 (ECAN Control 2) ...................................... 225
CiEC (ECAN Transmit/Receive Error Count) ........... 231
CiFCTRL (ECAN FIFO Control) ............................... 227
CiFEN1 (ECAN Acceptance Filter Enable)............... 233
CiFIFO (ECAN FIFO Status) .................................... 228
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 237,
CiINTE (ECAN Interrupt Enable) .............................. 230
CiINTF (ECAN Interrupt Flag) .................................. 229
CiRXFnEID (ECAN Acceptance Filter n
CiRXFnSID (ECAN Acceptance Filter n
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 240
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 240
CiRXMnEID (ECAN Acceptance Filter Mask n
CiRXMnSID (ECAN Acceptance Filter Mask n
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 241
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 241
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 243,
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 242
CiVEC (ECAN Interrupt Code) ................................. 226
CLKDIV (Clock Divisor) ............................................ 147
CORCON (Core Control) ...................................... 30, 93
DCICON1 (DCI Control 1) ........................................ 248
DCICON2 (DCI Control 2) ........................................ 249
DCICON3 (DCI Control 3) ........................................ 250
DCISTAT (DCI Status) ............................................. 251
DMACS0 (DMA Controller Status 0) ........................ 136
DMACS1 (DMA Controller Status 1) ........................ 138
DMAxCNT (DMA Channel x Transfer Count) ........... 135
DMAxCON (DMA Channel x Control)....................... 132
DMAxPAD (DMA Channel x Peripheral Address) .... 135
DMAxREQ (DMA Channel x IRQ Select) ................. 133
DMAxSTA (DMA Channel x RAM Start Address A) . 134
DMAxSTB (DMA Channel x RAM Start Address B) . 134
DSADR (Most Recent DMA RAM Address) ............. 139
I2CxCON (I2Cx Control)........................................... 209
I2CxMSK (I2Cx Slave Mode Address Mask)............ 213
I2CxSTAT (I2Cx Status) ........................................... 211
238
Extended Identifier) .......................................... 237
Standard Identifier) ........................................... 236
Extended Identifier) .......................................... 239
Standard Identifier) ........................................... 239
244, 246
DS70292D-page 395
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