ATMEGA165PV-8AU Atmel, ATMEGA165PV-8AU Datasheet - Page 209
ATMEGA165PV-8AU
Manufacturer Part Number
ATMEGA165PV-8AU
Description
IC AVR MCU 16K 8MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165PV-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Controller Family/series
AVR MEGA
No. Of I/o's
54
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA165PV-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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21.6
8019K–AVR–11/10
Changing Channel or Reference Selection
Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 21-7. ADC Timing Diagram, Free Running Conversion
Table 21-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
ADC Conversion Time
MUX and REFS
Update
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
Conversion
Complete
3
One Conversion
Sample &
Hold
11
4
Sample & Hold (Cycles from
Start of Conversion)
12
5
6
13
7
One Conversion
Next Conversion
1
13.5
1.5
Sign and MSB of Result
LSB of Result
2
8
2
MUX and REFS
Update
9
3
10
Conversion
Complete
Sample & Hold
11
4
12
Conversion Time (Cycles)
ATmega165P
13
Sign and MSB of Result
13.5
LSB of Result
25
13
Next Conversion
1
Prescaler
Reset
2
209
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