ATMEGA165PV-8AU Atmel, ATMEGA165PV-8AU Datasheet
ATMEGA165PV-8AU
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ATMEGA165PV-8AU Summary of contents
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... I/O and Packages – 54 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega165PV MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega165P MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
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Pin Configurations Figure 1-1. Pinout ATmega165P DNC 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) ...
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Overview The ATmega165P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut- ing powerful instructions in a single clock cycle, the ATmega165P achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega165P is a powerful microcontroller that provides a highly flex- ible and cost effective solution to many embedded control applications. ...
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Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics ...
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The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165P as listed in Chapter 2.2.8 ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8019K–AVR–11/10 ATmega165P 7 ...
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About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in ...
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AVR CPU Core 5.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...
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The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are ...
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Figure 5-3. Register Operands Fetch ALU Operation Execute 5.5 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts ...
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Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be ...
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Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C ...
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The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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AVR Memories This section describes the different memories in the ATmega165P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega165P features an EEPROM Memory for data storage. All ...
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SRAM Data Memory Figure 6-2 The ATmega165P is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space ...
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Figure 6-3. 6.3 EEPROM Data Memory The ATmega165P contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential). See register bit: 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no ...
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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 8019K–AVR–11/10 ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ...
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EEPROM Write During Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation ...
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General Purpose I/O Registers The ATmega165P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Sta- tus Flags. General Purpose I/O Registers within ...
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Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- ...
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System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...
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Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. C1 and C2 should always be ...
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The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 7-6. Table 7-6. CKSEL0 Notes: 7.6 Low-frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use ...
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Figure 7-3. Table 7-8. Crystals specifying load capacitance (CL) higher than 6.5 pF, require external capacitors applied as described in To find suitable load capacitance for a 32.768 kHz crysal, please consult the crystal datasheet. The Low-frequency Crystal Oscillator must ...
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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 7-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 7-4. When this ...
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Timer/Counter Oscillator ATmega165P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See crystal requirements. ATmega165P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs ...
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Register Description 7.11.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...
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The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue ...
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Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is enabled, it will keep on running during ...
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Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
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Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ...
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Register Description 8.9.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...
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Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be ...
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System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 9-1. BODLEVEL [2..0] 9.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the ...
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Figure 9-2. TIME-OUT INTERNAL Figure 9-3. TIME-OUT INTERNAL 9.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is not ...
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Brown-out Detection ATmega165P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger ...
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Internal Voltage Reference ATmega165P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.3.1 Voltage Reference Enable Signals and Start-up Time ...
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Figure 9-7. 9.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 9.4.1.1 Safety Level 1 In this mode, the ...
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Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: 8019K–AVR–11/10 (1) ; Reset WDT wdr ; Write logical one to WDCE and WDE in r16, WDTCR ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi ...
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Register Description 9.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...
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Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATmega165P. For a general explanation of the AVR interrupt handling, refer to page 12. 10.1 Interrupt Vectors in ATmega165P Table 10-1. Vector No ...
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If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table, see “MCUCR – MCU Control Register” on page To avoid unintentional changes of Interrupt Vector tables, ...
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Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret C ...
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External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as outputs. This feature provides ...
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Register Description 11.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 ...
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Bit 0 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled. The Interrupt Sense Control0 bits ...
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PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 ...
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I/O-Ports 12.1 Overiew All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 12-2. General Digital I/O Pxn Note: 12.2.1 Configuring the Pin Each port pin ...
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Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 12.2.3 Switching Between ...
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Figure 12-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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Assembly Code Example C Code Example unsigned char i; Note: 12.2.5 ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in all ...
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Table 12-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • OC2A/PCINT15, Bit 7 OC2, ...
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OC0A/PCINT12, Bit 4 OC0A, Output Compare Match A output: The PB4 pin can serve as an external output for the Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDB4 set (one)) to serve this ...
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Table 12-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 12-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8019K–AVR–11/10 Overriding Signals for Alternate Functions in PB7..PB4 PB7/OC2A/ PB6/OC1B/ ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-6. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • INT0 – Port D, ...
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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 12-8. Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit 7 PCINT7, Pin Change Interrupt Source ...
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XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper- ates in ...
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Table 12-10. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 12.3.4 Alternate Functions of Port F The Port F has an alternate function as analog input for ...
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TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be ...
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Table 12-13. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 12.3.5 Alternate Functions of Port G The alternate pin configuration is as follows: Table 12-14. Port G Pins ...
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Table 12-14 on page 77 ing signals shown in Table 12-15. Overriding Signals for Alternate Functions in PG4:PG3 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8019K–AVR–11/10 and Table 12-15 relates the alternate functions of ...
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Register Description 12.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...
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PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 12.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 12.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...
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PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 12.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 12.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write Initial ...
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Timer/Counter0 with PWM 13.1 Features • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • ...
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The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output ...
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Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...
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Figure 13-3. Output Compare Unit, Block Diagram top bottom FOCn The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double ...
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Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare unit, independently of whether ...
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The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. 13.6.1 Compare Output Mode and Waveform Generation The ...
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The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 13-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be ...
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In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of ...
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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to ...
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Figure 13-9 Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 13-10 Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 13-11 Figure 13-11. Timer/Counter Timing ...
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Register Description 13.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, ...
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Table 13-3 CTC mode (non-PWM). Table 13-3. COM0A1 Table 13-4 mode. Table 13-4. COM0A1 Note: Table 13-5 rect PWM mode. Table 13-5. COM0A1 Note: 8019K–AVR–11/10 shows the COM0A1:0 ...
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Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 13-6. CS02 external pin modes are used for ...
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TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register ...
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Timer/Counter1 14.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on ...
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Figure 14-1. 16-bit Timer/Counter Block Diagram Note: 14.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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Compare Units” on page 106. Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input ...
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Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 Figure 14-2. Counter Unit Block Diagram TEMP (8-bit) TCNTnH (8-bit) Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM1[3:0] bits. TOV1 can be used for generating a CPU interrupt. 14.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGM1[3:0]) bits must be set before the TOP ...
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Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is ...
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The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Compare Match Output Unit The Compare Output mode (COM1x[1:0]) bits have two functions. The Waveform Generator uses the COM1x[1:0] bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x[1:0] bits control the OC1x ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x[1: tells the Waveform Generator that no action on the OC1x Register ...
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The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 14-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...
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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM1[3: 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its ...
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ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure ...
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Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM1[3: 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, ...
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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord- ingly at the same timer clock cycle ...
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Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM1[3: provides a high resolution phase and frequency correct PWM wave- form generation option. ...
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Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). ...
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The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if ...
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Figure 14-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that ...
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Register Description 14.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A[1:0]: Compare Output Mode for Unit A • Bit 5:4 – COM1B[1:0]: Compare Output Mode for Unit B The COM1A[1:0] and ...
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Table 14-3 correct or the phase and frequency correct, PWM mode. Table 14-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM1[1:0]: Waveform Generation Mode Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the count- ing sequence ...
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Table 14-4. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 14.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...
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ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...
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TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register ...
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Timer/Counter0 and Timer/Counter1 Prescalers 15.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 15.2 Prescaler Reset The prescaler is free running, ...
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be ...
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Register Description 15.5.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...
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Timer/Counter2 with PWM and Asynchronous Operation 16.1 Features • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask ...
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Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 16-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com- pare (FOC2A) strobe bit in ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A[1: tells the Waveform Generator that no action on the OC2A Register ...
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Figure 16-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 16-6. Fast PWM Mode, ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM2[1: provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM ...
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The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between ...
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Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (f Figure 16-10 Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 16-11 Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 8019K–AVR–11/10 clk I/O clk ...
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Asynchronous operation of the Timer/Counter 16.9.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be ...
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Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ADC Noise ...
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Timer/Counter Prescaler Figure 16-12. Prescaler for Timer/Counter2 clk I/O TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a ...
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Register Description 16.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ...
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Table 16-3 or CTC mode (non-PWM). Table 16-3. COM2A1 Table 16-4 mode. Table 16-4. COM2A1 Note: Table 16-5 correct PWM mode. Table 16-5. COM2A1 Note: 8019K–AVR–11/10 shows the COM2A[1:0] bit functionality when ...
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Bit 2:0 – CS2[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 16-6. Table 16-6. CS22 16.11.2 TCNT2 – Timer/Counter Register ...
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TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is ...
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Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) ...
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SPI – Serial Peripheral Interface 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 17-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8019K–AVR–11/10 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8019K–AVR–11/10 (1) ; ...
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SS Pin Functionality 17.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 17-3 and nal, ensuring sufficient time ...
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Register Description 17.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...
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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...
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USART 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...
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Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. A simplified block diagram of the USART Transmit- ter is shown in Figure 18-1. USART Block Diagram Note: The dashed boxes ...
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AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, ...
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Figure 18-2. Clock Generation Logic, Block Diagram XCK Pin DDR_XCK Signal description: txclk rxclk xcki xcko fosc 18.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of ...
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Table 18-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRR Some examples of UBRR values for some system clock frequencies are found in page 179. ...
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Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...
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Figure 18-4. Frame Formats St ( IDLE The frame format used by the USART is set by the UCSZn2:0, UPM1n:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing ...
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USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...
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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: C Code Example #define FOSC 1843200// Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { ...
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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following ...
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Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether ...
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Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is over- ...
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Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn ...
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Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
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Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1n) bit is set. Type of Par- ity Check to be performed (odd or even) is selected by the UPM0n bit. When enabled, the Parity Checker ...
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Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames ...
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Figure 18-6. Sampling of Data and Parity Bit The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. ...
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The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow Table 18-2 that Normal Speed mode has higher toleration of baud rate ...
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The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The Receiver’s system ...
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When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5-bit to ...
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Table 18-5. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 18-6. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 18-7. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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Register Description 18.11.1 UDRn – USART I/O Data Register n Bit (0xC6) Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or ...
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Bit 5 – UDREn: USART Data Register Empty n The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The ...
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Bit 6 – TXCIEn: TX Complete Interrupt Enable n Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global ...
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Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
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Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and ...
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USI – Universal Serial Interface 19.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wake-up from All ...
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The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count ...
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Figure 19-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK The Three-wire mode timing is shown in erence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external ...
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The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
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Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim- iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 19-4. ...
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Figure 19-5. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be ...
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Start Condition Detector The start condition detector is shown in the range 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector ...
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Register Descriptions 19.5.1 USIDR – USI Data Register Bit (0xBA) Read/Write Initial Value The USI uses no buffering of the Serial Register, that is, when accessing the Data Register (USIDR) the Serial Register is accessed directly serial ...
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Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is ...
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Table 19-1. USIWM1 Note: • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the ...
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Table 19-2 used for the Shift Register and the 4-bit counter. Table 19-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the Shift Register to ...
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AC - Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the ...