AT89C5122D-RDRUM Atmel, AT89C5122D-RDRUM Datasheet - Page 157

• Manufacturer Part Number: AT89C5122D-RDRUM
• Description: IC 8051 MCU 32K CRAM USB 64-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-RDRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT89C5122D-RDRUMTR

Interrupt System
Introduction
Interrupt System
Description
4202F–SCR–07/2008
The AT83R5122, AT8xC5122/23 implements an interrupt controller with 15 inputs but
only 9 are used for :
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable registers (Table 98 on page 160 and Table 99 on page
161). These registers also contain a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on page
162 and Table 103 on page 164) and in the Interrupt Priority High register (Table 102 on
page 163 and Table 105 on page 166) shows the bit values and priority levels associ-
ated with each combination.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced first. Thus within each priority level there is a second priority structure deter-
mined by the polling sequence.
Table 97. Priority Level Bit Values
–
–
–
–
–
–
–
two external interrupts (INT0 and INT1)
two timer interrupts (timers 0, 1),
the UART interface
the SPI interface
the keyboard interface
the USB interface
the Smart Card Interface.
IPH.x
0
0
1
1
AT83R5122, AT8xC5122/23
IPL.x
0
1
0
1
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
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