PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 467

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Default System Clock ......................................................... 48
Development Support ...................................................... 413
Device Differences ........................................................... 464
Device Overview ................................................................ 11
Direct Addressing ............................................................... 93
E
ECCP2
Effect on Standard PIC Instructions ................................. 410
Electrical Characteristics .................................................. 417
Enhanced Capture/Compare/PWM (ECCP) .................... 193
Enhanced Universal Synchronous Asynchronous Receiver
ENVREG pin .................................................................... 358
Equations
Errata ................................................................................... 9
Ethernet Module ............................................................... 209
© 2009 Microchip Technology Inc.
Details on Individual Family Members ....................... 12
Features (100-Pin Devices) ....................................... 14
Features (64-Pin Devices) ......................................... 13
Features (80-Pin Devices) ......................................... 13
Pin Assignment ........................................................ 186
Requirements for Ethernet Transceiver External Mag-
Associated Registers ............................................... 208
Capture and Compare Modes .................................. 196
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and Program Memory Mode ...
ECCP2 Outputs and Program Memory Modes ........ 194
Enhanced PWM Mode ............................................. 197
Outputs and Configuration ....................................... 194
Pin Configurations for ECCP1 ................................. 195
Pin Configurations for ECCP2 ................................. 195
Pin Configurations for ECCP3 ................................. 196
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 196
Timer Resources ...................................................... 194
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 194
Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 334
A/D Minimum Charging Time ................................... 334
Calculating the A/D Minimum Required Acquisition Time
Random Access Address Calculation ...................... 243
Receive Buffer Free Space Calculation ................... 244
Associated Registers, Direct Memory Access Controller
Associated Registers, Flow Control ......................... 248
Associated Registers, Reception ............................. 245
Associated Registers, Transmission ........................ 245
Buffer and Buffer Pointers ........................................ 213
Buffer and Register Spaces ..................................... 212
Buffer Organization .................................................. 214
CRC ......................................................................... 238
Direct Memory Access Controller ............................ 255
Disabling .................................................................. 236
Duplex Mode Configuration and Negotiation ........... 246
Ethernet and Microcontroller Memory Relationship . 212
Ethernet Control Registers ....................................... 217
netics ............................................................... 451
194
256
Buffer Arbiter .................................................... 216
DMA Access .................................................... 216
Receive Buffer ................................................. 215
Transmit Buffer ................................................ 216
Checksum Calculations ................................... 256
Copying Memory .............................................. 255
.......................................................................... 334
PIC18F97J60 FAMILY
Ethernet Operation, Microcontroller Clock ......................... 45
EUSARTx
Flow Control ............................................................ 247
Initializing ................................................................. 235
Interrupts ................................................................. 229
Interrupts and Wake-on-LAN ................................... 234
LED Configuration ................................................... 210
MAC and MII Registers ........................................... 219
Magnetics, Termination and Other External Components
Oscillator Requirements .......................................... 210
Packet Format ......................................................... 237
Per-Packet Control Bytes ........................................ 239
PHSTAT Registers .................................................. 222
PHY Register Summary .......................................... 224
PHY Registers ......................................................... 222
PHY Start-up Timer ................................................. 210
Receive Filters ......................................................... 249
Resets ..................................................................... 257
Signal and Power Interfaces .................................... 210
Special Function Registers (SFRs) ......................... 217
Transmitting and Receiving Data ............................ 237
Asynchronous Mode ................................................ 315
Baud Rate Generator
Baud Rate Generator (BRG) ................................... 309
Synchronous Master Mode ...................................... 323
Broadcast ........................................................ 249
Hash Table ...................................................... 249
Magic Packet ................................................... 249
Multicast .......................................................... 249
Pattern Match .................................................. 249
Unicast ............................................................ 249
Microcontroller Reset ....................................... 257
Receive Only ................................................... 257
Transmit Only .................................................. 257
Packet Field Definitions ........................... 237–238
Reading Received Packets ............................. 243
Receive Buffer Space ...................................... 244
Receive Packet Layout .................................... 242
Receive Status Vectors ................................... 243
Receiving Packets ........................................... 242
Transmit Packet Layout ................................... 240
Transmit Status Vectors .................................. 241
Transmitting Packets ....................................... 239
Associated Registers, Receive ........................ 319
Associated Registers, Transmit ....................... 317
Auto-Wake-up on Sync Break Character ........ 320
Break Character Sequence ............................. 322
Receiver .......................................................... 318
Setting Up 9-Bit Mode with Address Detect .... 318
Transmitter ...................................................... 315
Operation in Power-Managed Modes .............. 309
Associated Registers ....................................... 310
Auto-Baud Rate Detect .................................... 313
Baud Rate Error, Calculating ........................... 310
Baud Rates, Asynchronous Modes ................. 311
High Baud Rate Select (BRGH Bit) ................. 309
Sampling ......................................................... 309
Associated Registers, Receive ........................ 326
Associated Registers, Transmit ....................... 324
Reception ........................................................ 325
Transmission ................................................... 323
......................................................................... 211
Receiving ................................................. 322
DS39762E-page 467