PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 115

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.6.3
Figure 7-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written based on the Least
Significant bit of the TBLPTR register.
FIGURE 7-3:
© 2009 Microchip Technology Inc.
Note 1:
PIC18F97J60
2:
3:
16-BIT BYTE SELECT MODE
A<19:16>
AD<15:8>
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
Upper order address lines are used only for 20-bit address width.
Demultiplexing is only required when multiple memory devices are accessed.
AD<7:0>
WRH
ALE
BA0
OE
UB
CE
I/O
LB
(2)
16-BIT BYTE SELECT MODE EXAMPLE
373
373
A<20:1>
A<20:1>
PIC18F97J60 FAMILY
138
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard, static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
(3)
A<x:1>
A<x:1>
CE
UB
A0
CE
BYTE/WORD
LB
OE WR
FLASH Memory
SRAM Memory
Address Bus
Data Bus
Control Lines
JEDEC Word
JEDEC Word
(1)
OE WR
D<15:0>
D<15:0>
DS39762E-page 115
(1)
D<15:0>
D<15:0>