PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 216

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

programmed as part of the receive FIFO buffer is consid-
managing where packets are located in the transmit
PIC18F97J60 FAMILY
18.2.1.3
Any space within the 8-Kbyte memory which is not
ered to be the transmit buffer. The responsibility of
buffer belongs to the application. Whenever the applica-
tion decides to transmit a packet, the ETXST and ETXND
Pointers are programmed with addresses specifying
where, within the transmit buffer, the particular packet to
transmit is located. The hardware does not check that the
start and end addresses do not overlap with the receive
buffer. To prevent buffer corruption, the firmware must not
transmit a packet while the ETXST and ETXND Pointers
are overlapping the receive buffer, or while the ETXND
Pointers are too close to the receive buffer. See
Section 18.5.2 “Transmitting Packets” for more
information.
18.2.1.4
The Ethernet buffer is clocked at one-half of the micro-
controller clock rate. Varying amounts of memory
access bandwidth are available depending on the clock
speed. The total bandwidth available, in bytes per sec-
ond, is equal to twice the instruction rate (2 * F
F
41.667 MHz, the total available memory bandwidth that
is available is 20.834 Mbyte/s. At an Ethernet signaling
rate of 10 Mbit/s, the Ethernet RX engine requires
1.25 Mbyte/s of buffer memory bandwidth to operate
without causing an overrun. If Full-Duplex mode is
used, an additional 1.25 Mbyte/s is required to allow for
simultaneous RX and TX activity.
Because of the finite available memory bandwidth, a
three-channel arbiter is used to allocate bandwidth
between the RX engine, the TX and DMA engines, and
the microcontroller’s CPU (i.e., the application access-
TABLE 18-2:
DS39762E-page 216
OSC
41.667
31.250
25.000
20.833
13.889
12.500
(MHz)
8.333
6.250
4.167
2.778
F
OSC
/2). For example, at a system clock speed of
Transmit Buffer
Buffer Arbiter and Access Arbitration
(MHz)
10.42
7.81
6.25
5.21
3.47
3.13
2.08
1.56
1.04
0.69
F
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BUFFER ARBITRATION RESTRICTIONS VS. CLOCK SPEED
Available Bandwidth (Mbyte/s)
20.83
15.63
12.50
10.42
Total
6.94
6.25
4.17
3.13
2.08
1.39
After RX
19.58
14.38
11.25
9.17
5.69
5.00
2.92
1.88
0.83
0.14
After TX
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18.33
13.13
10.00
4.44
3.75
1.67
0.63
7.92
< 0
< 0
, or
Access EDATA no more than once every 2 T
Access EDATA no more than once every 2 T
Access EDATA no more than once every 2 T
Access EDATA no more than once every 2 T
Access EDATA no more than once every 2 T
Access EDATA no more than once every 2 T
Access EDATA no more than once every 3 T
Access EDATA no more than once every 5 T
Do not use DMA, do not use full duplex,
access EDATA no more than once every 3 T
Do not use DMA, do not use full duplex,
access EDATA no more than once every 10 T
ing EDATA). The arbiter gives the EDATA register
accesses first priority, while all remaining bandwidth is
shared between the RX and TX/DMA blocks.
With arbitration, bandwidth limitations require that
some care be taken in balancing the needs of the mod-
ule’s hardware with that of the application. Accessing
the EDATA register too often may result in the RX or TX
blocks causing a buffer overrun or underrun, respec-
tively. If such a memory access failure occurs, the
BUFER bit (ESTAT<6>) and either the TXERIF or
RXERIF interrupt flag becomes set, and a TX or RX
interrupt occurs (if enabled). In either case, the current
packet will be lost or aborted.
To eliminate the risk of lost packets, run the microcon-
troller core at higher speeds. Following the arbitration
restrictions shown in Table 18-2 will prevent memory
access failures from occurring. Also, avoid using seg-
ments of application code which perform back-to-back
accesses of the EDATA register. Instead, insert one or
more instructions (including NOP instructions) between
each read or write to EDATA.
18.2.1.5
The integrated DMA controller must read from the
buffer when calculating a checksum, and it must read
and write to the buffer when copying memory. The DMA
follows the same wrapping rules as previously
described for the receive buffer. While it sequentially
reads, it will be subject to a wrapping condition at the
end of the receive buffer. All writes it does will not be
subject to any wrapping conditions. See Section 18.9
“Direct Memory Access Controller” for more
information.
to Prevent Underrun/Overrun
Application Restrictions
DMA Access to the Buffer
© 2009 Microchip Technology Inc.
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